All The Claims

1. A balance (10) for weighing blister packs (50) in the microgram weight range,
with a balance pan (12, 14) on which the at least one blister pack (50) to be weighed can be placed,
with a blister pack (50) made of chargeable material,
characterized in that
the balance pan (12, 14) is designed in such a way that field forces (70) caused by an electric field act practically exclusively on the balance pan (12, 14), which field can be generated by an electrically charged blister pack (50) lying on the balance pan.
2. The balance as claimed in claim 1,
characterized in that
a body (18) interacting with an electric field (70) emanating from the at least one blister pack (50) is secured as a load on the balance pan (12, 14).
3. The balance as claimed in one of the preceding claims,
characterized in that
the balance pan (12, 14) andor the body (18) is grounded.
4. The balance as claimed in one of the preceding claims,
characterized in that
the body is designed as a plate.
5. The balance as claimed in one of claims 1 through 3,
characterized in that
the body is designed as a cage (18), such that
the at least one blister pack (50) resting on the balance pan (12, 14) is present in the inside (34) of the cage (18).
6. The balance as claimed in claim 5,
characterized in that
the cage (18) has an opening through which the at least one blister pack (50) to be weighed can be guided into the cage (18) and can be removed again from the cage (18).
7. The balance as claimed in one of claims 4 through 6,
characterized in that
the plate or the walls of the cage (18) have material cutouts (80).
8. The balance as claimed in claim 7,
characterized in that
the plate or the walls of the cage (18) are made of perforated sheet metal or wire lattice.
9. The balance as claimed in one of the preceding claims,
characterized in that
the balance pan (12, 14) has a three-point support (12) for the at least one blister pack (50) to be weighed.
10. The balance as claimed in claim 9,
characterized in that
the three legs (12.1, 12.2, 12.3) of the three-point support (12) are guided through cutouts (22, 24, 26) in the bottom plate (20) of the cage (18).
11. The balance as claimed in one of the preceding claims,
characterized in that
the body, in particular the cage (18), has a three-point support for the at least one blister pack (50) to be weighed.
12. The balance as claimed in claim 11,
characterized in that
the three legs of the three-point support are raised parts of the bottom plate (20) of the cage.
13. The balance as claimed in one of the preceding claims,
characterized in that
a windproof housing (82) is provided at least for the area of the balance pan (12, 14), such that
this housing (82) acts as a wind protection for the at least one blister pack (50) lying on the balance pan.
14. The balance as claimed in claim 13,
characterized in that
the windproof housing is electrically conductive and is grounded.
15. The balance as claimed in claim 14,
characterized in that
the windproof housing (82) is made of grounded metal or of glass metallized to be electrically conductive.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for finding an optimized filter parameters design for a digital IF programmable downconverter, comprises the following steps:
(1) receiving an input specification, said input specification comprising an input signal sampling rate, an input data rate, an oversampling factor R, an available number of Halfband decimation filters, a passband frequency, a stopband frequency, a passband ripple, a stopband attenuation and a optimal filter parameter satisfying said input specification;
(2) determining if said oversampling factor R is equal to 1;
(3) obtaining an largest available number nHB of Halfband decimation filters and setting an initial value of nHB equal to a total of Halfband decimation filters;
(4) obtaining an largest available first number of Halfband decimation filters satisfying said input specification and determining if re-sampling FIR filter is necessary;
(5) obtaining an optimized combination of Halfband decimation filters satisfying said input specification;
(6) obtaining a total n of window function for designing filters;
(7) obtaining a window function index j and setting said windows function index to 1; and
(8) obtaining a programmable FIR filter satisfying said input specification.
2. The method of claim 1, wherein the step (4) further comprises the following steps:
A: estimating a decimation factor M based on said largest available number nHB of Halfband decimation filters and obtaining a minimum decimation factor MCIC,min of CIC decimation filter;
B: determining if said minimum decimation factor MCIC,min of CIC decimation filter is equal to said decimation factor M; and
C: obtaining a decimation factor threshold MV of CIC decimation filter and determining if said minimum decimation factor MCIC,min of CIC decimation filter is larger or equal to said decimation factor threshold MV of CIC decimation filter.
3. The method of claim 2, wherein in step C if MCIC,min is less than MV, subtracting 1 from said largest available number nHB of Halfband decimation filters and determining if said nHB is larger or equal to O.
4. The method of claim 2, wherein said decimation factor M obtained from said largest available number nHB of Halfband decimation filters is further obtained by dividing said input signal sampling rate by twice said input data rate, then divided by a decimation factor MnHB of Halfband decimation filter having said largest available number nHB, wherein MnHB=2nHB.
5. The method of claim 2, wherein said minimum decimation factor MCIC,min of CIC decimation filter is less than or equal to a positive integer of said decimation factor M obtained from said largest available number nHB of Halfband decimation filter.
6. The method of claim 1, wherein the step (5) further comprises the following steps:
A: estimating a decimation factor M1 based on a combination number nHB,i of Halfband decimation filters having a priority index i and obtaining a decimation factor MCIC of CIC decimation filter;
B: obtaining a combination threshold MORF of Halfband decimation filters having said priority index i; and
C: determining if said decimation factor MCIC of CIC decimation filter is larger or equal to said combination threshold MORF of Halfband decimation filters having said priority index i.
7. The method of claim 6, wherein if step C is true, then determining if said decimation factor MCIC of CIC decimation filter is equal to said decimation factor M1.
8. The method of claim 6, wherein said decimation factor M1 obtained from said combination number nHB,i of Halfband decimation filters having a priority index I is further obtained from dividing said input signal sampling rate by twice said input data rate, then divided by said decimation factor MnHB,i of Halfband decimation filter having said combination number nHB,i of Halfband decimation filters and said priority index i, wherein MnHB,i=2nHB,i.
9. The method of claim 6, wherein said decimation factor MCIC is less than or equal to a largest positive integer of said decimation factor M1 obtained from said combination number nHB,i of Halfband decimation filter having said priority index i.
10. The method of claim 1, wherein the step (8) generating a coefficient of said programmable FIR filter based on said window function of window function index j and determining if a synthesized frequency response of said digital IF programmable down-converter satisfying said input specification.
11. The method of claim 10, wherein if said synthesized frequency response is not satisfying said input specification, add 1 to said window function index j and determine if said window function index j is greater than said total n of window function.
12. A method for finding an optimized filter parameters design for a digital IF programmable downconverter, comprises the following steps:
(1) receiving an input specification, said input specification comprising an input signal sampling rate, an input data rate, an oversampling factor R, an available number of Halfband decimation filters, a passband frequency, a stopband frequency, a passband ripple, a stopband attenuation and a optimal filter parameter satisfying said input specification;
(2) determining if said oversampling factor R is equal to 1;
(3) obtaining an largest available number nHB of Halfband decimation filters and setting an initial value of nHB equal to a total of Halfband decimation filters;
(4) obtaining an largest available first number of Halfband decimation filters satisfying said input specification and determining if re-sampling FIR filter is necessary;
(5) obtaining an optimized combination of Halfband decimation filters satisfying said input specification;
(6) obtaining a total n of window function for designing filters;
(7) obtaining a window function index j and setting said windows function index to 1; and
(8) obtaining a programmable FIR filter satisfying said input specification; wherein the step (4) further comprises the following steps:
A: estimating a decimation factor M based on said largest available number nHB of Halfband decimation filters and obtaining a minimum decimation factor MCIC,min of CIC decimation filter;
B: determining if said minimum decimation factor MCIC,min of CIC decimation filter is equal to said decimation factor M; and
C: obtaining a decimation factor threshold MV of CIC decimation filter and determining if said minimum decimation factor MCIC,min of CIC decimation filter is larger or equal to said decimation factor threshold MV of CIC decimation filter; wherein the obtaining said decimation factor threshold MV of CIC decimation filter step further comprises the following steps:
(1) obtaining a total clock cycle CLKR of re-sampling FIR filters and Halfband interpolation filters based on an existing index q and a oversampling factor R, wherein
COKR=CLKres\xd7q+NL
(2) obtaining a threshold CLKTH of re-sampling FIR filters and Halfband interpolation filters by dividing said total clock cycle CLKR of re-sampling FIR filters and Halfband interpolation filters by said decimation factor MnHB of Halfband decimation filter having said largest available number nHB;
(3) estimating a minimum clock cycle CLKnHB,min of all combinations of Halfband decimation filter having said largest available number nHB by:
CLKnHB
,

mm
=

{
\u2211

i
=
1

nHB

\u2062
\u2062
(
TDi
–
3
4
+
2

)
2

i
\u2062
\u2062
1
,

nHB
>
0
1
,
\u2062

nHB
=
0
;

\u2062
(4) obtaining said decimation factor threshold MV of CIC decimation filter by determining a maximum between said threshold CLKTH of re-sampling FIR filters and Halfhand interpolation filters and said minimum clock cycle CLKnHB,min of all combinations of Halfband decimation filter having said largest available number nHB.
13. A method for finding an optimized filter parameters design for a digital IF programmable downconverter, comprises the following steps:
(1) receiving an input specification, said input specification comprising an input signal sampling rate, an input data rate, an oversampling factor R, an available number of Halfband decimation filters, a passband frequency, a stopband frequency, a passband ripple, a stopband attenuation and a optimal filter parameter satisfying said input specification;
(2) determining if said oversampling factor R is equal to 1;
(3) obtaining an largest available number nHB of Halfband decimation filters and setting an initial value of nHB equal to a total of Halfband decimation filters;
(4) obtaining an largest available first number of Halfband decimation filters satisfying said input specification and determining if re-sampling FIR filter is necessary;
(5) obtaining an optimized combination of Halfband decimation filters satisfying said input specification;
(6) obtaining a total n of window function for designing filters;
(7) obtaining a window function index j and setting said windows function index to 1; and
(8) obtaining a programmable FIR filter satisfying said input specification; wherein the step (5) further comprises the following steps:
A: estimating a decimation factor M1 based on a combination number nHB,i of Halfband decimation filters having a priority index i and obtaining a decimation factor MCIC of CIC decimation filter;
B: obtaining a combination threshold MORF of Halfband decimation filters having said priority index i; and
C: determining if said decimation factor MCIC of CIC decimation filter is larger or equal to said combination threshold MORF of Halfband decimation filters having said priority index i; wherein said combination threshold MORF of Halfband decimation filters having said priority index i is an overclock rate factor of said combinations of Halfband decimation filters having priority index i, said MORF is obtained by:
M
ORF

=
\u2211

i
=
k

1

\u2062
\u2062
(
HBDFi
)

\u2062

2
\u2211

j
=
k

1

\u2062
\u2062
HBDFj
\u2062
(
TD
i

–
3

4

+
2

)
2

nHB
,
1

1. An integrated circuit for use in a mobile TV receiver, the integrated circuit comprising:
one or more input stages for receiving respective RF signals, including mobile TV signals;
a first signal processing path for performing low IF demodulation of the RF signals;
a second signal processing path for performing IQ demodulation of the RF signals;
a control unit arranged to selectively connect the one or more input stages to the first signal processing path or to the second signal processing path; and
output circuitry connected to the first and second signal processing paths, wherein the control unit is arranged to determine whether the output circuitry outputs signals that have been obtained from the one or more RF signals by IF demodulation or alternatively by IQ demodulation.
2. The integrated circuit according to claim 1 in which the one or more input stages each include a filter for removing frequencies received that are not mobile TV signals or that are generated by the mobile TV receiver device.
3. The integrated circuit according to claim 1 in which the control unit is operative to disable at least one section of the integrated circuit, to reduce the power consumption of that section.
4. The integrated circuit according to claim 3 in which the control unit is operative to disable selectively the first or second processing paths.
5. The integrated circuit according to claim 3 in which the control unit is operative to disable one or more of the input stages.
6. The integrated circuit according to claim 3 in which the control unit disables the section by setting a pin connected to the section to ground voltage.
7. The integrated circuit according to claim 6 in which the control unit, together with disabling the section, also turns off a circuit for delivering power to the section.
8. The integrated circuit according to claim 3 in which the control unit is operative based on a clock signal to turn at least one section of the integrated circuit on or off according to a timing present in the RF signal.
9. The integrated circuit according to claim 3 in which the control unit is operative to modify the operation of at least one other component of the integrated circuit selectively between a first operation state with higher power consumption and a second operation state of lower power consumption.
10. An integrated circuit according to claim 1 comprising at least two automatic gain control circuits, a first wideband automatic gain control circuit operative to control the gain of the input stages, and a second narrowband automatic gain control circuit operative to control the amplitude of the output of the output circuitry.
11. The integrated circuit according to claim 1 further comprising a phase-lock loop unit, a crystal oscillator, and oscillating signal transmission circuitry for transmitting an oscillating signal generated using the crystal oscillator out of the integrated circuit.
12. The integrated circuit according to claim 1 further comprising a phase-lock loop unit and oscillating signal receiver for receiving a crystal oscillation signal input for driving the phase-lock loop unit.
13. The integrated circuit according to claim 1 further comprising a phase-lock loop unit, a crystal oscillator, oscillating signal receiver for receiving a crystal oscillation signal input for driving the phase-lock loop unit, and oscillating signal transmission circuitry for transmitting an oscillating signal generated using the crystal oscillator out of the integrated circuit, and control circuitry for selecting whether the phase-lock loop unit is driven based on a crystal oscillation signal input.
14. The integrated circuit according to claim 11 in which the crystal oscillator generates a signal in the range of about 1 to 60 MHz.
15. The integrated circuit according to claim 14 in which the crystal oscillator generates a signal of at least 16 MHz.
16. The integrated circuit according to claim 1 in which the input stages each comprise a variable amplifier or a phase and time delay variation unit.
17. A mobile TV receiver device comprising:
one or more input stages for receiving respective RF signals, including mobile TV signals;
a first signal processing path for performing low IF demodulation of the RF signals;
a second signal processing path for performing IQ demodulation of the RF signals;
a control unit arranged to selectively connect the one or more input stages to the first signal processing path or to the second signal processing path;
output circuitry connected to the first and second signal processing paths, wherein the control unit is arranged to determine whether the output circuitry outputs signals that have been obtained from the one or more RF signals by IF demodulation or alternatively by IQ demodulation;
one or more antennas that generate one or more RF signals and transmit them to respective ones of the input stages of the integrated circuit,
a base-band processing unit that receives the output of the output circuitry of the integrated circuit, and performs base-band processing to produce TV signals; and
a screen that receives the TV signals and uses them to generate TV images.
18. The mobile TV receiver device according to claim 17 in which there are a plurality of antennas generating respective RF signals and transmitting them to respective ones of the input stages.
19. The mobile TV receiver device according to claim 17 further comprising:
partitioning circuitry for partitioning the RF signals from at least one of the antennas into multiple components, the components being respective frequency ranges; and
transmission circuitry for transmitting the components to respective ones of the input stages.
20. The mobile TV receiver device according to claim 17 in which at least one of the antennas includes at least two portions for receiving radio signals with different polarizations, and which includes transmission circuitry for transmitting the received radio signals to different respective ones of the input stages.
21. The mobile TV receiver device according to claim 17 further comprising circuitry for generating and transmitting RF signals of at least one transmission frequency, the receiver device including one or more filters for filtering out the transmission frequency from the RF signals received by the antennas.
22. The mobile device according to claim 21 wherein the one or more filters are located within the integrated circuit on each of the input stages.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

What is claimed is:

1. An imaging lens of fixed focal length formed of only two lens components, in order from the object side, as follows:
an aperture diaphragm;
a first lens component having positive refractive power, having a concave lens surface on the object side, and having at least one aspheric lens surface; and
a second lens component having positive refractive power and having at least one aspheric lens surface;
wherein the following conditions are satisfied:
f1f2<3.0CL2DL2>0.8
where
f1 is the focal length of said first lens component,
f2 is the focal length of said second lens component,
CL2 is the thickness of said second lens component, measured parallel to the optical axis, at a distance from the optical axis determined by the smaller maximum optically effective diameter in said imaging lens of the two lens surfaces of said second lens component, and
DL2 is the thickness of said second lens component at the optical axis of the imaging lens.
2. The imaging lens of claim 1, wherein:
said first lens component includes a first lens element; and
said second lens component includes a second lens element.
3. The imaging lens of claim 1, wherein:
said first lens component consists of a first lens element; and
said second lens component consists of a second lens element.
4. The imaging lens of claim 1, wherein:
said first lens component has a meniscus shape;
said second lens component has a meniscus shape with its convex lens surface on the object side; and
the concave lens surface of said second lens component is formed so that its negative refractive power increases as the distance from the optical axis of the imaging lens increases.
5. The imaging lens of claim 2, wherein:
said first lens component has a meniscus shape;
said second lens component has a meniscus shape with its convex lens surface on the object side; and
the concave lens surface of said second lens component is formed so that its negative refractive power increases as the distance from the optical axis of the imaging lens increases.
6. The imaging lens of claim 2, wherein:
said first lens element has a meniscus shape;
said second lens element has a meniscus shape with its convex lens surface on the object side; and
the concave lens surface of said second lens element is formed so that its negative refractive power increases as the distance from the optical axis of the imaging lens increases.
7. The imaging lens of claim 3, wherein:
said first lens element has a meniscus shape;
said second lens element has a meniscus shape with its convex lens surface on the object side; and
the concave lens surface of said second lens element is formed so that its negative refractive power increases as the distance from the optical axis of the imaging lens increases.