All The Claims

1. An apparatus for fabricating a flat panel display device comprising:
an imprinting mold connected to a substrate to form a thin film pattern on the substrate;
a first adsorption pad to vacuum-adsorb the center of the imprinting mold;
a second adsorption pad to vacuum-adsorb the periphery of the imprinting mold; and
a connector connected to vacuum pins to vertically move in different regions of the first and second adsorption pads.
2. The apparatus according to claim 1, wherein the connector is formed in the center of the first adsorption pad.
3. The apparatus according to claim 1, wherein the connector is formed in the periphery of the second adsorption pad such that it is adjacent to the edge of the imprinting mold.
4. The apparatus according to claim 1, wherein the first and second adsorption pads take the shape of a circle or polygon.
5. A method for fabricating a flat panel display device comprising:
joining an imprinting mold having a protrusion and a groove to a substrate to form a thin film pattern on the substrate; and
separating the imprinting mold from the substrate using a first adsorption pad to vacuum-adsorb the center of the imprinting mold, a second adsorption pad to vacuum-adsorb the periphery of the imprinting mold, and a connector connected to vacuum pins to vertically move in different regions of the first and second adsorption pads.
6. The method according to claim 5, wherein the connector is formed in the center of the first adsorption pad.
7. The method according to claim 5, wherein the connector is formed in the periphery of the second adsorption pad such that it is adjacent to the edge of the imprinting mold.
8. The method according to claim 5, wherein the first and second adsorption pads take the shape of a circle or polygon.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A method for taking a digital picture of an image, the method comprising the steps of:
recording a first plurality of pixel values representing the image;
recording a second plurality of pixel values representing the image; and
processing the first and second plurality of pixel values in a compressed domain to generate a third plurality of pixel values.
2. The method in accordance with claim 1 wherein the step of recording the first plurality of pixel values comprises the steps of:
measuring a light condition for a center portion of the image; and
recording the first plurality of pixel values in accordance with optimized recording for the light condition for the center portion of the image, and

wherein the step of recording the second plurality of pixel values comprises the steps of:
measuring a light condition for a portion of the image other than the center portion; and
recording the second plurality of pixel values in accordance with optimized recording for the light condition of the portion of the image other than the center portion.
3. The method in accordance with claim 2 wherein the step of recording the first plurality of pixel values in accordance with optimized recording for the light condition for the center portion of the image comprises the step of recording the first plurality of pixel values for a first predetermined exposure time, and wherein the step of recording the second plurality of pixel values in accordance with optimized recording for the light condition of a portion of the image other than the center portion comprises the step of recording the second plurality of pixel values for a second predetermined exposure time, wherein the first predetermined exposure time is defined to optimize bright light conditions at the center portion, and wherein the second predetermined exposure time is defined to maximize a dynamic range of the image.
4. The method in accordance with claim 1 wherein the step of processing the first and second plurality of pixel values to generate a third plurality of pixel values comprises the steps of:
determining a center image boundary in response to the first and second plurality of pixel values; and
generating the third plurality of pixel values in the compressed domain in response to the first plurality of pixel values, the second plurality of pixel values and the center image boundary.
5. The method in accordance with claim 4 wherein the step of generating the third plurality of pixel values comprises the steps of:
replacing ones of the second pixel values within the center image boundary with ones of the first pixel values within the center image boundary; and
defining a smooth transition boundary in the compressed domain which includes the center image boundary.
6. The method in accordance with claim 5 wherein the step of defining the smooth transition boundary in the compressed domain comprises the step of defining the smooth transition boundary in accordance with a filtering technique, the smooth transition boundary including the center image boundary.
7. The method in accordance with claim 6 wherein the step of defining the smooth transition boundary in accordance with a filtering technique comprises the step of defining the smooth transition boundary in accordance with a filtering technique selected from the group of filtering techniques comprising bandpass filtering, low pass filtering, and low pass filtering utilizing a Fourier expansion method.
8. The method in accordance with claim 5 wherein the step of determining a center image boundary comprises the step of determining the center image boundary by cosine transformation of the first and second plurality of pixel values.
9. The method in accordance with claim 1 further comprising the step of applying Huffman coding to the third plurality of pixel values.
10. The method in accordance with claim 1 wherein the step of recording the first plurality of pixel values comprises the step of recording compressed image data for the first plurality of pixel values to generate a first compressed image data file, and wherein the step of recording the second plurality of pixel values comprises the step of recording compressed image data for the second plurality of pixel values to generate a second compressed image data file, and wherein the step of processing the first and second plurality of pixel values in a compressed domain to generate the third plurality of pixel values comprises the step of processing the first and second compressed image data files to generate a third compressed image data file.
11. The method in accordance with claim 10 wherein the step of recording compressed image data for the first plurality of pixel values comprises the step of recording the compressed image data in accordance with a JPEG compression algorithm by measuring DC values and AC-sum values to generate the first compressed image data file, and wherein the step of recording compressed image data for the second plurality of pixel values comprises the step of recording the compressed image data in accordance with the JPEG compression algorithm by measuring DC values and AC-sum values to generate the second JPEG compressed image data file, the step of processing the first and second compressed image data files comprising the step of processing the first and second compressed image data files at an intermediate step within the JPEG compression algorithms to generate the third compressed image data file.
12. A digital camera module comprising:
a plurality of light sensitive pixel elements;
a first memory buffer;
a second memory buffer; and
a controller coupled to the plurality of light sensitive pixel elements and the first and second memory buffers, the controller recording a first plurality of pixel values representing an image by activating the plurality of light sensitive pixel elements in a first predetermined manner and storing the first plurality of pixel values in the first buffer, and the controller recording a second plurality of pixel values representing the image by activating the plurality of light sensitive pixel elements in a second predetermined manner and storing the second plurality of pixel values in the second buffer, wherein the controller processes the first and second plurality of pixel values in a compressed domain to generate a third plurality of pixel values.
13. The digital camera module in accordance with claim 12 wherein the controller activates the plurality of light sensitive pixel elements in the first predetermined manner by measuring a light condition for a center portion of the image and activating the plurality of light sensitive pixel elements for optimized recording for the light condition measured for the center portion of the image.
14. The digital camera module in accordance with claim 13 wherein the controller activates the plurality of light sensitive pixel elements in the second predetermined manner by measuring a light condition for a portion of the image other than the center portion and activating the plurality of light sensitive pixel elements for optimized recording for the light condition measured for the portion of the image other than the center portion.
15. The digital camera module in accordance with claim 14 wherein the controller activates the plurality of light sensitive pixel elements for optimized recording for the light condition measured for the center portion of the image by providing a first timing signal to the plurality of light sensitive pixel elements for activation thereof for a first predetermined exposure time and activates the plurality of light sensitive pixel elements for optimized recording for the light condition measured for the portion of the image other than the center portion by providing a second timing signal to the plurality of light sensitive pixel elements for activation thereof for a second predetermined exposure time.
16. The digital camera module in accordance with claim 12 further comprising a lens system for focusing light passing through the lens system onto the plurality of light sensitive pixel elements, wherein the plurality of light sensitive pixel elements are arranged in an array within a light path of light passing through the lens system.
17. The digital camera module in accordance with claim 12 wherein the controller records the first plurality of pixel values in the compressed domain by activating the plurality of light sensitive pixel elements in the first predetermined manner to measure compressed image data for the plurality of light sensitive pixel elements to generate a first compressed image data file, the controller storing the first compressed image data file in the first buffer, and wherein the controller records the second plurality of pixel values in the compressed domain by activating the plurality of light sensitive pixel elements in the second predetermined manner to measure compressed image data for the plurality of light sensitive pixel elements to generate a second compressed image data file, the controller storing the second compressed image data file in the second buffer, and wherein the controller processes the first and second plurality of pixel values in the compressed domain to generate the third plurality of pixel values by processing the first and second compressed image data files to generate a third compressed image data file.
18. A mobile communication device comprising:
a plurality of light sensitive pixel elements;
a first memory buffer;
a second memory buffer;
a controller coupled to the plurality of light sensitive pixel elements and the first and second memory buffers, the controller recording a first plurality of pixel values representing the image by activating the plurality of light sensitive pixel elements in a first predetermined manner and storing the first plurality of pixel values in the first buffer, and the controller recording a second plurality of pixel values representing the image by activating the plurality of light sensitive pixel elements in a second predetermined manner and storing the second plurality of pixel values in the second buffer, wherein the controller processes the first and second plurality of pixel values in a compressed domain to generate a third plurality of pixel values;
a storage device coupled to the exposure controller for storing the digital image as image information;
a communication controller coupled to the storage device for selectively retrieving the image information corresponding to the digital image; and
transmitting circuitry coupled to the communication controller for transmitting the digital image when the image information corresponding to the digital image is provided to the transmitting circuitry by the communication controller.
19. The mobile communication device in accordance with claim 18 wherein the controller records the first plurality of pixel values in the compressed domain by activating the plurality of light sensitive pixel elements in the first predetermined manner to measure compressed image data for the plurality of light sensitive pixel elements to generate a first compressed image data file, the controller storing the first compressed image data file in the first buffer, and wherein the controller records the second plurality of pixel values in the compressed domain by activating the plurality of light sensitive pixel elements in the second predetermined manner to measure compressed image data for the plurality of light sensitive pixel elements to generate a second compressed image data file, the controller storing the second compressed image data file in the second buffer, and wherein the controller processes the first and second plurality of pixel values in the compressed domain to generate the third plurality of pixel values by processing the first and second compressed image data files to generate a third compressed image data file.
20. The mobile communication device in accordance with claim 18 further comprising a lens system for focusing light passing through the lens system onto the plurality of light sensitive pixel elements, wherein the plurality of light sensitive pixel elements are arranged in an array within a light path of light passing through the lens system.

1. A method of adapting a rate of an output signal to a rate of an output medium, said method comprising:
providing a media access controller comprising an internal clock;
inputting an external clock signal into said media access controller;
providing a register at an output of said media access controller for outputting data to an external device, said register comprising a first input configured to control an output of the register and a second input configured to control an input to said register;
providing said external clock signal to said first input of said register;
providing an internal clock signal from said internal clock to said second input of said register;
measuring a capacity of said register; and
substituting said internal clock signal with said external clock signal when said capacity reaches a predetermined level such that said external clock signal is provided to both said first input and said second input of said register.
2. The method of claim 1, further comprising continuing said internal clock signal when said capacity falls below said predetermined level such that said internal clock signal is provided to said second input of said register and said external clock signal is provided to said first input of said register.
3. The method of claim 1, wherein providing a register comprises providing a FIFO as said register.
4. The method of claim 1, wherein inputting an external clock signal comprises matching said external clock with a speed of said external device.
5. The method of claim 1, further comprising matching the internal clock to match said external clock.
6. An apparatus to adapt a rate of an output signal to a rate of an output medium, said apparatus comprising:
a register configured to output data to an external device, said register comprising a first input configured to control an output of the register and a second input configured to control an input to said register;
a receiver configured to accept a signal from an external clock over the output medium and to provide said external clock signal to said first input of said register; and
an internal clock configured to provide an internal clock signal from said internal clock to said second input of said register,
wherein said register is further configured to measure a capacity of said register, and
substitute said internal clock signal with said external clock signal when said capacity reaches a predetermined level such that said external clock signal is provided to both to said first input and to said second input of said register.
7. The apparatus of claim 6, wherein said register is further configured to use said internal clock signal when said capacity falls below said predetermined level such that said internal clock signal is provided to said second input of said register and said external clock signal is provided to said first input of said register.
8. The apparatus of claim 6, wherein said register comprises a FIFO.
9. The apparatus of claim 6, wherein said external clock is matched to a speed of said external device.
10. The apparatus of claim 6, wherein internal clock is further configured to:
receive said external clock signal, and
match said external clock.
11. An apparatus for adapting a rate of an output signal to a rate of an output medium, said apparatus comprising:
register means for outputting data to an external device, said register means comprising first input means for controlling an output of the register and second input means for controlling an input to said register;
receiver means for accepting a signal from an external clock means over the output medium and for providing said external clock signal to said first input means of said register means; and
an internal clock means for providing an internal clock signal from said internal clock to said second input of said register,
wherein said register means is further configured to measure a capacity of said register means and to substitute said internal clock signal with said external clock signal when said capacity reaches a predetermined level such that said external clock signal is provided to both said first input means and said second input means of said register means.
12. The apparatus of claim 11, wherein said register means is further configured to use said internal clock signal when said capacity falls below said predetermined level such that said internal clock signal is provided to said second input means of said register means and said external clock signal is provided to said first input means of said register means.
13. The apparatus of recited in claim 11, wherein said register means comprises a FIFO.
14. The apparatus of recited in claim 11, wherein said external clock means is matched to a speed of said external device.
15. The apparatus of recited in claim 11, wherein internal clock means is further configured to receive said external clock signal, and match said external clock.
16. A computer readable medium having recorded and stored thereon instructions for adapting a rate of an output signal to a rate of an output medium that, when executed, perform the actions of:
providing a media access controller comprising an internal clock;
inputting an external clock signal into said media access controller;
providing a register at an output of said media access controller for outputting data to an external device, said register comprising a first input configured to control an output of the register and a second input configured to control an input to said register;
providing said external clock signal to said first input of said register;
providing an internal clock signal from said internal clock to said second input of said register;
measuring a capacity of said register; and
substituting said internal clock signal with said external clock signal when said capacity reaches a predetermined level such that said external clock signal is provided to both said first input and said second input of said register.
17. The computer readable medium of claim 16 further comprising instructions that, when executed, perform the actions of continuing said internal clock signal when said capacity falls below said predetermined level such that said internal clock signal is provided to said second input of said register and said external clock signal is provided to said first input of said register.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A multi-layer device comprising:
a substrate;
at least one electrical component located on the substrate;
an electrically conductive bond layer, formed on the substrate and surrounding the electrical component; and
an encasing layer, wherein the encasing layer is bonded to the bond layer to form a sealed cavity encasing the electrical component therein.
2. A device according to claim 1, wherein the encasing layer is anodically bonded to the bond layer to form the sealed cavity.
3. A device according to claim 1, wherein the substrate comprises an electrical conductor, positioned in isolation from the surface provided to receive the bond layer, to connect the component with an external contact pad.
4. A device according to claim 3, wherein the conductor is formed from at least one conducting layer coupled with conducting plugs.
5. A device according to claim 4, wherein the conducting layer is surrounded by dielectric layers.
6. A device according to claim 1, wherein the component is CMOS or BiCMOS circuitry.
7. A device according to claim 1, wherein the component is a pressure sensor or an inertial sensor.
8. A device according to claim 1, further comprising a conductive shielding layer which is placed on the glass wafer and connected to the substrate, in order to protect the device from the electric field generated during anodic bonding.
9. A device according to claim 1, wherein a second encasing layer is bonded to a second surface of the substrate to form a second sealed cavity.
10. A multi-layer device comprising:
a substrate including a support region;
at least one electrical component located within the support region;
an electrically conductive layer surrounding the support region; and
an encasing layer including a cavity,

wherein the electrically conductive layer is configured to bond the encasing layer to the substrate such that the at least one electrical component is sealed within the cavity.