All The Claims

1. A hinge assembly, comprising:
a socket member attached to an end of a temple of a pair of eyeglasses; and
a ball member attached to a temple region of a main frame of the pair of eyeglasses;
wherein the ball member is configured to be received and held within the socket member; and
wherein each of: (a) the socket member is resiliently attached to the end of the temple; and (b) the ball member is resiliently attached to the temple region of the main frame.
2. The hinge assembly of claim 1, further comprising a housing having a first cavity into which at least a portion of the socket member is received, wherein the housing is attached to the end of the temple.
3. The hinge assembly of claim 2, further comprising a socket member projection, wherein the socket member projection extends, when the socket member is at least partially within the first cavity, into a second cavity in the housing.
4. The hinge assembly of claim 3, further comprising a spring disposed at least partially within the second cavity, wherein a partition separates the first cavity from the second cavity, wherein the socket member projection extends from the first cavity to the second cavity through an opening in the partition, and wherein the spring biases the socket member towards the partition.
5. The hinge assembly of claim 1, further comprising a housing having a cavity into which at least a portion of a pin of the ball member is received, wherein the housing is attached to the temple region of the main frame.
6. The hinge assembly of claim 5, further comprising a spring disposed at least partially within the cavity, wherein a partition at least partially defines the cavity, wherein the ball member pin extends into the cavity through an opening in the partition, and wherein the spring biases the ball member towards the partition.
7. The hinge assembly of claim 1, wherein the socket member includes at an end thereof a plurality of flexible fingers, and wherein the fingers are configured to flex open to allow the ball member to enter the socket member.
8. The hinge assembly of claim 7, wherein each of the fingers includes at a free end thereof a flange, and wherein each flange helps to retain the ball member within the socket member when the fingers flex closed.
9. The hinge assembly of claim 1, wherein the socket member includes at least one slot for guiding movement of a ball member pin extending from the ball member.
10. The hinge assembly of claim 9, wherein the socket member includes two essentially orthogonal slots for guiding movement of the ball member pin extending from the ball member.
11. A hinge assembly, comprising:
a socket member attached to a temple region of a main frame of a pair of eyeglasses; and
a ball member attached to an end of a temple of the pair of eyeglasses;
wherein the ball member is configured to be received and held within the socket member; and
wherein each of: (a) the socket member is resiliently attached to the temple region of the main frame; and (b) the ball member is resiliently attached to the end of the temple.
12. The hinge assembly of claim 11, further comprising a housing having a first cavity into which at least a portion of the socket member is received, wherein the housing is attached to the temple region of the main frame.
13. The hinge assembly of claim 12, further comprising a socket member projection, wherein the socket member projection extends, when the socket member is at least partially within the first cavity, into a second cavity in the housing.
14. The hinge assembly of claim 13, further comprising a spring disposed at least partially within the second cavity, wherein a partition separates the first cavity from the second cavity, wherein the socket member projection extends from the first cavity to the second cavity through an opening in the partition, and wherein the spring biases the socket member towards the partition.
15. The hinge assembly of claim 11, further comprising a housing having a cavity into which at least a portion of a pin of the ball member is received, wherein the housing is attached to the end of the temple.
16. The hinge assembly of claim 15, further comprising a spring disposed at least partially within the cavity, wherein a partition at least partially defines the cavity, wherein the ball member pin extends into the cavity through an opening in the partition, and wherein the spring biases the ball member towards the partition.
17. The hinge assembly of claim 11, wherein the socket member includes at an end thereof a plurality of flexible fingers, and wherein the fingers are configured to flex open to allow the ball member to enter the socket member.
18. The hinge assembly of claim 17, wherein each of the fingers includes at a free end thereof a flange, and wherein each flange helps to retain the ball member within the socket member when the fingers flex closed.
19. The hinge assembly of claim 11, wherein the socket member includes at least one slot for guiding movement of a ball member pin extending from the ball member.
20. The hinge assembly of claim 19, wherein the socket member includes two essentially orthogonal slots for guiding movement of the ball member pin extending from the ball member.
21. A pair of hinge assemblies, comprising:
(a) a first hinge assembly, comprising:
a socket member attached to an end of a right temple of a pair of eyeglasses; and
a ball member attached to a right temple region of a main frame of the pair of eyeglasses;
wherein the ball member is configured to be received and held within the socket member; and
wherein each of: (a) the socket member is resiliently attached to the end of the right temple; and (b) the ball member is resiliently attached to the right temple region of the main frame; and

(b) a second hinge assembly, comprising:
a socket member attached to an end of a left temple of the pair of eyeglasses; and
a ball member attached to a left temple region of the main frame of the pair of eyeglasses;
wherein the ball member is configured to be received and held within the socket member; and
wherein each of: (a) the socket member is resiliently attached to the end of the left temple; and (b) the ball member is resiliently attached to the left temple region of the main frame.
22. A pair of hinge assemblies, comprising:
(a) a first hinge assembly, comprising:
a socket member attached to a right temple region of a main frame of a pair of eyeglasses; and
a ball member attached to an end of a right temple of the pair of eyeglasses;
wherein the ball member is configured to be received and held within the socket member; and
wherein each of: (a) the socket member is resiliently attached to the right temple region of the main frame; and (b) the ball member is resiliently attached to the right temple; and

(b) a second hinge assembly, comprising:
a socket member attached to a left temple region of the main frame of the pair of eyeglasses; and
a ball member attached to an end of a left temple of the pair of eyeglasses;
wherein the ball member is configured to be received and held within the socket member; and
wherein each of: (a) the socket member is resiliently attached to the left temple region of the main frame; and (b) the ball member is resiliently attached to the left temple.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A system for remotely accessing data from an access control module over an Internet Protocol (IP) communications network, the system comprising:
a host device configured to interface over the communications network with a network server remotely located from the host device and configured to interface locally with the access control module, the access control module being non-addressable on the communications network, the host device comprising a table populated by information provided by the access control module in response to a query from the host device,
wherein the host device provides at least a portion of the table to the network server through the communications network in response to a server query to an IP network address of the host device, and
wherein the host device is configured to send the query to a Uniform Resource Locator (URL) associated with the information provided by the access control module, the URL being previously provided to the host device in an application information resource.
2. The system of claim 1, wherein the network server is included in a cable headend.
3. The system of claim 1, wherein the access control module comprises a separate card, and host device interfaces with the separate card through a Personal Computer Memory Card International Association (PCMCIA) interface.
4. The system of claim 3, wherein the separate card is configured as a CABLECARD\u2122 according to the OPENCABLE\u2122 standard.
5. The system of claim 4, wherein the table is included in a management information base (MIB) of the host device.
6. The system of claim 1, wherein the information provided by the access control module is HyperText Markup Language (HTML) formatted.
7. A system for remotely accessing information of a cablecard module configured to control access to programming content, the system comprising:
a cable headend computer configured to receive a management information base (MIB) from a host device, corresponding to the cablecard module, over an Internet Protocol (IP) network, in response to a first query from the headend computer to the host device, the cablecard module having no IP network address, the host device comprising an IP addressable device and the cablecard module comprising a non-IP addressable device,
wherein the MIB comprises diagnostic information provided by the cablecard module in response to a second query from the host device to the cablecard module, and
wherein the host device is configured to send the second query to a Uniform Resource Locator (URL) associated with the information provided by the cablecard module, the URL being previously provided to the host device in an application information resource.
8. The system of claim 7, wherein the information provided by the cablecard module is HyperText Markup Language (HTML) formatted.
9. The system of claim 8, wherein the headend computer is further configured to parse the diagnostic information provided by the cablecard module for analysis.
10. The system of claim 9, further comprising:
a display configured to display at least a portion of the parsed information; and
a database configured to store at least a portion of the parsed information.
11. The system of claim 7, wherein the cablecard module comprises a CABLECARD\u2122 in accordance with the OPENCABLE\u2122 standard.
12. The system according to claim 11, wherein the MIB is Simple Network Management Protocol (SNMP) formatted.
13. A method for remotely accessing information on a cablecard, configured to provide access control of programming content, the method comprising:
querying a host device, associated with the cablecard, over an Internet Protocol (IP) network;
receiving data from a management information base (MIB) of the host device over the IP network in response to the query, the MIB data comprising information provided by the cablecard in response to a host query from the host device to the cablecard, the host device having an IP network address and the cablecard having no IP network address; and
parsing the received cablecard information for at least one of displaying and storing at least a portion of the cablecard information,
wherein the host query is sent to a Uniform Resource Locator (URL) associated with the information provided by the cablecard, the URL being previously provided to the host device in an application information resource.
14. The method of claim 13, wherein the MIB is Simple Network Management Protocol (SNMP) formatted.
15. The method of claim 14, wherein the cablecard information is included in an ocStbHostCCAppInfoEntry of an ocStbHostCCAppInfoTable of the SNMP MIB.

1. A method of cleaning residue from a surface comprising:
(a) providing a cellulosic wiper comprising from about 90% by weight to about 25% by weight pulp-derived papermaking fiber and from about 10% to about 75% by weight fibrillated regenerated cellulosic microfiber having a characteristic CSF value of less than 175 ml;
(b) applying the wiper to a residue-bearing surface with pressure and wiping the surface under pressure to remove residue therefrom.
2. The method of cleaning residue from a surface according to claim 1, wherein the surface is glass.
3. The method of cleaning residue from a surface according to claim 1, wherein the surface is metal.
4. The method of cleaning residue from a surface according to claim 1, wherein the surface is ceramic.
5. The method of cleaning residue from a surface according to claim 1, wherein the surface is a countertop surface.
6. The method of cleaning residue from a surface according to claim 1, wherein the surface is an appliance surface.
7. The method of cleaning residue from a surface according to claim 1, wherein the surface is a floor surface.
8. The method of cleaning residue from a surface according to claim 1, wherein the method is effective to remove residue from the surface such that the surface has less than 1 gm2 of residue after wiping with the wiper.
9. The method of cleaning residue from a surface according to claim 1, wherein the method is effective to remove residue from the surface such that the surface has less than 0.5 gm2 of residue after wiping with the wiper.
10. The method of cleaning residue from a surface according to claim 1, wherein the method is effective to remove residue from the surface such that the surface has less than 0.25 gm2 of residue after wiping with the wiper.
11. The method of cleaning residue from a surface according to claim 1, wherein the method is effective to remove residue from the surface such that the surface has less than 0.1 gm2 of residue after wiping with the wiper.
12. The method of cleaning residue from a surface according to claim 1, wherein the method is effective to remove residue from the surface such that the surface has less than 0.01 gm2 of residue after wiping with the wiper.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A memory circuit comprising:
a first plurality of memory arrays disposed in a column fashion;
a first plurality of keepers, each of which is electrically coupled with a corresponding one of the first plurality of memory arrays; and
a first current limiter electrically coupled with and shared by the first plurality of keepers.
2. The memory circuit of claim 1, wherein the first plurality of memory arrays each includes at least one memory cell including a read port, the read port is configured to allow a first current flowing through the read port if the read port is turned on and a voltage drop across the read port during a sensing period, the first current limiter is configured to control a second current flowing through the first current limiter during the sensing period, and the first current is larger than the second current during the sensing period.
3. The memory circuit of claim 1, wherein the first current limiter comprises a first transistor and the first transistor is turned on during at least one of a sensing period and a precharge period.
4. The memory circuit of claim 3, wherein the first plurality of keepers each comprises:
at least one second transistor; and
a logic gate, wherein an output end of the logic gate is electrically coupled with a gate of the at least one second transistor, and at least one input end of the logic gate is electrically coupled with at least one drain of the at least one second transistor.
5. The memory circuit of claim 4, wherein the at least one second transistor each is a core transistor, and a channel length of the first transistor is larger than a channel length of the at least one second transistor.
6. The memory circuit of claim 4, wherein the logic gate is a NOT gate and the at least one second transistor includes a single transistor.
7. The memory circuit of claim 4, wherein the logic gate is an NAND gate and the at least one second transistor includes two or more transistors.
8. The memory circuit of claim 1, further comprising:
a second plurality of memory arrays disposed in a column fashion; and
a second plurality of keepers each of which is electrically coupled with a corresponding one of the second plurality of memory arrays, wherein the second plurality of keepers are electrically coupled with the first current limiter.
9. The memory circuit of claim 1, further comprising:
a third plurality of memory arrays disposed in a column fashion, wherein each of the third plurality of memory arrays is disposed adjacent a corresponding one of the first plurality of memory arrays;
a third plurality of keepers each of which is electrically coupled with a corresponding one of the third plurality of memory arrays; and
a second current limiter electrically coupled with the third plurality of keepers.
10. A memory circuit comprising:
a first current limiter, wherein the first current limiter comprises a first transistor;
a first plurality of memory arrays disposed in a column fashion; and
a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays, the first plurality of keepers being electrically coupled with the first current limiter, wherein the at least one first plurality of keepers each comprises:
at least one second transistor; and
a logic gate, wherein an output end of the logic gate is electrically coupled with a gate of the at least one second transistor, and at least one input end of the logic gate is electrically coupled with at least one drain of the at least one second transistor.
11. The memory circuit of claim 10, wherein the first plurality of memory arrays each includes at least one memory cell including a read port, the read port is configured to allow a first current flowing through the read port if the read port is turned on and a voltage drop across the read port during a sensing period, the first current limiter is configured to control a second current flowing through the first current limiter during the sensing period, and the first current is larger than the second current during the sensing period.
12. The memory circuit of claim 10, wherein the first transistor is turned on during at least one of a sensing period and a precharge period.
13. The memory circuit of claim 10, wherein the at least one second transistor each is a core transistor, and a channel length of the first transistor is larger than a channel length of the at least one second transistor.
14. The memory circuit of claim 10, further comprising
a second plurality of memory arrays disposed in a column fashion; and
a second plurality of keepers each of which is electrically coupled with a corresponding one of the second plurality of memory arrays, wherein the second plurality of keepers are electrically coupled with the first current limiter.
15. The memory circuit of claim 10, further comprising
a third plurality of memory arrays disposed in a column fashion, wherein each of the third plurality of memory arrays is disposed adjacent a corresponding one of the first plurality of memory arrays;
a third plurality of keepers each of which is electrically coupled with a corresponding one of the third plurality of memory arrays; and
a second current limiter coupled with the third plurality of keepers.
16. A memory circuit comprising:
a first current limiter configured to control a first current flowing through the first current limiter during a sensing period, wherein the first current limiter comprises a first transistor;
a first plurality of memory arrays disposed in a column fashion, wherein the first plurality of memory arrays each includes at least one memory cell including a read port, and the read port is configured to allow a first current flowing through the read port if the read port is turned on and a voltage drop across the read port during the sensing period;
a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays, wherein the at least one first plurality of keepers each comprises:
at least one second transistor, wherein at least one source end of the at least one second transistor is electrically coupled with the first current limiter; and
a logic gate, wherein an output end of the logic gate is electrically coupled with a gate of the at least one second transistor, and at least one input end of the logic gate is electrically coupled with at least one drain of the at least one second transistor.
17. The memory circuit of claim 16, wherein the first transistor is turned on during at least one of a sensing period and a precharge period.
18. The memory circuit of claim 16, wherein the at least one second transistor each is a core transistor, and a channel length of the first transistor is larger than a channel length of the at least one second transistor.
19. The memory circuit of claim 16, wherein the logic gate is a NOT gate and the at least one second transistor includes a single transistor.
20. The memory circuit of claim 16, wherein the logic gate is an NAND gate and the at least one second transistor includes two or more transistors.