1. A clock selection circuit that receives first and second clock signals, and selects and outputs one of the clock signals, the clock selection circuit comprising:
a first control circuit that generates a first clock control signal activated for a first specified period, and outputs a first gated clock signal based on a delayed first clock signal during the first specified period in response to at least one of a control signal and a first disable signal;
a second control circuit that generates a second clock control signal activated for a second specified period, and outputs a second gated clock signal based on a delayed second clock signal during the second specified period in response to at least one of the inverted control signal and a second disable signal;
a first disable signal generating circuit that generates the first disable signal by delaying the second clock control signal for a specified cycle duration of the delayed first clock signal;
a second disable signal generating circuit that generates the second disable signal by delaying the first clock control signal for a specified cycle duration of the delayed second clock signal; and
a logic circuit that generates an output clock signal by performing a logic operation on the first and second gated clock signals.
2. The clock selection circuit of claim 1, wherein the first control circuit comprises:
a first clock control circuit that generates the first clock control signal in response to the control signal and the first disable signal, wherein said first clock control signal is activated during the first specified period;
a first delay circuit that delays the first clock signal and outputs the delayed first clock signal; and
a first gating circuit that outputs the delayed first clock signal as the first gated clock signal during the first specified period of the first clock control signal.
3. The clock selection circuit of claim 2, wherein the first clock control circuit comprises:
a NOR gate that receives the control signal, the first disable signal, and the second clock control signal; and
a flip-flop that receives an output signal of the NOR gate and outputs the first clock control signal.
4. The clock selection circuit of claim 2, wherein the first gating circuit comprises a NAND gate that receives the first clock control signal and the delayed first clock signal and outputs the first gated clock signal.
5. The clock selection circuit of claim 1, wherein the second control circuit comprises:
a second clock control circuit that generates the second clock control signal in response to the inverted control signal and the second disable signal, wherein said second clock control signal is activated during the second specified period;
a second delay circuit that delays the second clock signal and outputs the delayed second clock signal; and
a second gating circuit that outputs the delayed second clock signal as the second gated clock signal during the second specified period of the second clock control signal.
6. The clock selection circuit of claim 5, wherein the second clock control circuit comprises:
a NOR gate that receives the inverted control signal, the second disable signal, and the first clock control signal; and
a flip-flop that receives an output signal of the NOR gate and outputs the second clock control signal.
7. The clock selection circuit of claim 5, wherein the second gating circuit comprises a NAND gate that receives the second clock control signal and the delayed second clock signal, and outputs the second gated clock signal.
8. The clock selection circuit of claim 1, wherein the first disable signal generating circuit comprises a plurality of flip-flops connected in series, the flip-flops each having a clock port for receiving the delayed first clock signal as input, wherein the second clock control signal is input to a first flip-flop among the plurality of flip-flops, and the first disable signal is output from a last flip-flop among the plurality of flip-flops.
9. The clock selection circuit of claim 1, wherein the second disable signal generating circuit comprises a plurality of flip-flops connected in series, the flip-flops each having a clock port for receiving the delayed second clock signal as input, the first clock control signal is input to a first flip-flop among the plurality of flip-flops, and the second disable signal is output from a last flip-flop among the plurality of flip-flops.
10. The clock selection circuit of claim 1, wherein the logic circuit comprises a NAND gate that receives the first and second gated clock signals and outputs the output clock signal.
11. The clock selection circuit of claim 1, wherein the first control circuit outputs the first gated clock signal only during the first specified period, and wherein the second control circuit outputs the second gated clock signal only during the second specified period.
12. A clock selection circuit that receives first and second clock signals, and selects and outputs one of the clock signals, the clock selection circuit comprising:
a first clock control circuit that generates a first clock control signal having a first activation section of a specified length, said first clock control signal being generated in response to at least one of a control signal and a first disable signal;
a first delay circuit that delays the first clock signal and outputs a delayed first clock signal;
a first gating circuit that outputs the delayed first clock signal as a first gated clock signal during the first activation section of the first clock control signal;
a second clock control circuit that generates a second clock control signal having a second activation section of a specified length, said second clock control signal being generated in response to at least one of the control signal inverted and a second disable signal;
a second delay circuit that delays the second clock signal and outputs a delayed second clock signal;
a second gating circuit that outputs the delayed second clock signal as a second gated clock signal during the second activation section of the second clock control signal;
a first disable signal generating circuit that generates the first disable signal by delaying the second clock control signal for a specified cycle duration of the delayed first clock signal, said first disable signal being generated in response to the delayed first clock signal;
a second disable signal generating circuit that generates the second disable signal by delaying the first clock control signal for a specified cycle duration of the delayed second clock signal, said second disable signal being generated in response to the delayed second clock signal; and
a logic circuit that generates an output clock signal by performing a logic operation on the first and second gated clock signals.
13. The clock selection circuit of claim 12, wherein the first clock control circuit comprises:
an NOR gate that receives the control signal, the first disable signal, and the second clock control signal; and
a flip-flop that receives an output signal of the NOR gate and outputs the first clock control signal.
14. The clock selection circuit of claim 12, wherein the first gating circuit comprises a NAND gate that receives the first clock control signal and the delayed first clock signal and outputs the first gated clock signal.
15. The clock selection circuit of claim 12, wherein the second clock control circuit comprises:
an NOR gate that receives the inverted control signal, the second disable signal, and the first clock control signal; and
a flip-flop that receives an output signal of the NOR gate and outputs the second clock control signal.
16. The clock selection circuit of claim 12, wherein the second gating circuit comprises a NAND gate that receives the second clock control signal and the delayed second clock signal and outputs the second gated clock signal.
17. The clock selection circuit of claim 12, wherein the first disable signal generating circuit comprises a plurality of flip-flops connected in series, the flip-flops each having a clock port for receiving the delayed first clock signal, wherein the second clock control signal is input to a first flip-flop among the plurality of flip-flops, and the first disable signal is output from a last flip-flop among the plurality of flip-flops.
18. The clock selection circuit of claim 12, wherein the second disable signal generating circuit comprises a plurality of flip-flops connected in series, the flip-flops each having a clock port for receiving the delayed second clock signal, wherein the first clock control signal is input to a first flip-flop among the plurality of flip-flops, and the second disable signal is output from a last flip-flop among the plurality of flip-flops.
19. The clock selection circuit of claim 12, wherein the logic circuit comprises a NAND gate that receives the first and second gated clock signals and outputs the output clock signal.
20. A digital processing system, comprising:
a first clock signal source;
a second clock signal source;
a digital processing circuit operating with at least one of the clock frequencies of said first clock signal source and said second clock signal source; and
a clock selection circuit receiving first and second clock signals from the first and second clock signal sources respectively, selecting one of the clock signals, and outputting the selected clock signal to the digital processing circuit, wherein the clock selection circuit comprises,
a first control circuit that generates a first clock control signal activated for a first specified period, and outputs a first gated clock signal based on a delayed first clock signal during the first specified period in response to at least one of a control signal and a first disable signal;
a second control circuit that generates a second clock control signal activated for a second specified period, and outputs a second gated clock signal based on a delayed second clock signal, during the second specified period in response to at least one of the control signal inverted and a second disable signal;
a first disable signal generating circuit that generates the first disable signal by delaying the second clock control signal for a specified cycle duration of the delayed first clock signal;
a second disable signal generating circuit that generates the second disable signal by delaying the first clock control signal for a specified cycle duration of the delayed second clock signal; and
a logic circuit that generates an output clock signal by performing a logic operation on the first and second gated clock signals.
21. The digital processing system of claim 20, wherein the first control circuit comprises:
a first clock control circuit that generates the first clock control signal in response to the control signal and the first disable signal, wherein said first clock control signal is activated during the first specified period;
a first delay circuit that delays the first clock signal and outputs the delayed first clock signal; and
a first gating circuit that outputs the delayed first clock signal as the first gated clock signal during the first specified period of the first clock control signal.
22. The digital processing system of claim 21, wherein the first clock control circuit comprises:
an NOR gate that receives the control signal, the first disable signal, and the second clock control signal; and
a flip-flop that receives an output signal of the NOR gate and outputs the first clock control signal.
23. The digital processing system of claim 21, wherein the first gating circuit comprises a NAND gate that receives the first clock control signal and the delayed first clock signal and outputs the first gated clock signal.
24. The digital processing system of claim 20, wherein the second control circuit comprises:
a second clock control circuit that generates the second clock control signal in response to the inverted control signal and the second disable signal, wherein said second clock control signal is activated during the second specified period;
a second delay circuit that delays the second clock signal and outputs the delayed second clock signal; and
a second gating circuit that outputs the delayed second clock signal as the second gated clock signal during the second specified period of the second clock control signal.
25. The digital processing system of claim 24, wherein the second clock control circuit comprises:
an NOR gate that receives the inverted control signal, the second disable signal, and the first clock control signal; and
a flip-flop that receives an output signal of the NOR gate and outputs the second clock control signal in response to the second clock signal.
26. The digital processing system of claim 24, wherein the second gating circuit comprises a NAND gate that receives the second clock control signal and the delayed second clock signal, and outputs the second gated clock signal.
27. The digital processing system of claim 20, wherein the first disable signal generating circuit comprises a plurality of flip-flops connected in series, the flip-flops each having a clock port into which the delayed first clock signal is input, the second clock control signal is input to a first flip-flop among the plurality of flip-flops, and the first disable signal is output from a last flip-flop among the plurality of flip-flops.
28. The digital processing system of claim 20, wherein the second disable signal generating circuit comprises a plurality of flip-flops connected in series, the flip-flops each having a clock port into which the delayed second clock signal is input, the first clock control signal is input to a first flip-flop among the plurality of flip-flops, and the second disable signal is output from a last flip-flop among the plurality of flip-flops.
29. The digital processing system of claim 20, wherein the logic circuit comprises a NAND gate that receives the first and second gated clock signals and outputs the output clock signal.
30. The clock selection circuit of claim 19, wherein the first control circuit outputs the first gated clock signal only during the first specified period, and wherein the second control circuit outputs the second gated clock signal only during the second specified period.
31. A clock selection circuit comprising:
a first control circuit that generates a first clock control signal based on a control signal and at least one of a first disable signal, a first clock signal and a second clock control signal, and wherein said first control circuit generates a first gated clock signal based on the first clock control signal and a delayed first clock signal, the delayed first clock signal not being used as the clock signal for any flip-flop of the first control circuit;
a second control circuit that generates the second clock control signal based on the control signal inverted and at least one of a second disable signal, a second clock signal and the first clock control signal, and wherein said second control circuit generates a second gated clock signal based on the second clock control signal and a delayed second clock signal, the delayed second clock signal not being used as the clock signal for any flip-flop of the second control circuit; and
a logic circuit that generates an output clock signal by performing a logic operation on the first and second gated clock signals.
32. The clock selection circuit of claim 31, wherein said logic circuit includes a NAND gate.
33. The clock selection circuit of claim 31, further comprising:
a first disable signal generating circuit that generates the first disable signal by delaying the second clock control signal for a specified cycle duration of the delayed first clock signal;
a second disable signal generating circuit that generates the second disable signal by delaying the first clock control signal for a specified cycle duration of the delayed second clock signal.
34. A method of selecting and outputting one of a first clock signal and a second clock signal comprising:
generating a first clock control signal based on a control signal and at least one of a first disable signal, the first clock signal and a second clock control signal;
generating a first gated clock signal based on the first clock control signal and a delayed first clock signal;
generating the second clock control signal based on an inverted control signal and at least one of a second disable signal, the second clock signal and the first clock control signal;
generating a second gated clock signal based on the second clock control signal and a delayed second clock signal;
generating the first disable signal by delaying the second clock control signal for a specified cycle duration of the delayed first clock signal;
generating the second disable signal by delaying the first clock control signal for a specified cycle duration of the delayed second clock signal; and
performing a logic operation on the first and second gated clock signals; and generating an output clock signal based on said logic operation.
35. The method of claim 34, wherein performing said logic operation includes performing a NAND operation.
36. A digital processing system, comprising:
a first clock signal source;
a second clock signal source;
a digital processing circuit operating with at least one of said first clock signal source and said second clock signal source; and
a clock selection circuit receiving the first and second clock signals from the first and second clock signal sources, selecting one of said first and second clock signals, and outputting the selected clock signal to the digital processing circuit, wherein said clock selection circuit receives a control signal and generates two gated clock signals based on the control signal and an inverted control signal, and wherein the clock selection circuit further generates a first disable signal by delaying a second clock control signal for a specified cycle duration of a delayed first clock signal and generates a second disable signal by delaying a first clock control signal for a specified cycle duration of a delayed second clock signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed as new and is desired to be secured by Letter Patent of the United States is:
1. An image forming apparatus, comprising:
an image forming mechanism configured to perform an image forming operation for forming an image on a recording sheet;
a process cartridge configured to contain material used to make said image visible, said process cartridge being detachably installed in said apparatus;
a card inlet configured to receive an electronic money integrated circuit card, said card inlet including a data input and output port for connecting to said electronic money integrated circuit card when it is inserted in said card inlet, said electronic money integrated circuit card including an integrated circuit chip dedicated to an electronic money application; and
a controlling mechanism configured to control said image forming operation performed by said image forming mechanism, said controlling mechanism including an integrated circuit chip dedicated to said electronic money application, said controlling mechanism capable of communicating for monetary information with said electronic money integrated circuit card via said data input and output ports.
2. An image forming apparatus, comprising:
an image forming mechanism configured to perform an image forming operation for forming an image on a recording sheet;
a process cartridge configured to contain material used to make said image visible, said process cartridge being detachably installed in said apparatus, said process cartridge including an electronic money application unit which includes an integrated circuit chip dedicated to an electronic money application; and
a controlling mechanism configured to control said image forming operation performed by said image forming mechanism, said controlling mechanism including an integrated circuit chip dedicated to said electronic money application, said controlling mechanism capable of communicating for monetary information with said process cartridge with said integrated circuit chips dedicated for said electronic money application.
3. An image forming apparatus as defined in claim 2, wherein said electronic money application unit of said process cartridge further includes a data input and output port for electrically connecting to an electronic money integrated circuit card to enable said electronic money application unit to communicate for said monetary information with said electronic money integrated circuit card.
4. An image forming apparatus as defined in claim 2, wherein said monetary information handled by said electronic money application unit of said process cartridge includes property information for identifying said process cartridge.
5. An image forming apparatus as defined in claim 4, wherein said property information included in said monetary information includes a part number, a manufacturing number, and a price of said process cartridge.
6. An image forming apparatus as defined in claim 3, wherein said electronic money application unit of said process cartridge further includes a battery powering said electronic money application unit to communication for said monetary information with said electronic money integrated circuit card via said data input and output ports.
7. An image forming apparatus as defined in claim 2, further comprising a communication mechanism configured to perform communication for said monetary information using said integrated circuit chip dedicated for said electronic money application with an external host computer located at a remote control center.
8. An image forming apparatus as defined in claim 7, wherein said external host computer stores a data base holding history information for a plurality of image forming apparatuses.
9. An image forming apparatus as defined in claim 7, wherein said communication mechanism performs said communications with said external host computer at one or more predetermined times of a day on as-needed basis.
10. An image forming apparatus as defined in claim 7, wherein said communication mechanism performs said communications via a telephone network.
11. An image forming apparatus as defined in claim 7, wherein said communication mechanism performs said communications via the Internet using Internet functions of E-mail or a file transfer protocol.
12. An information control system, comprising:
an image forming apparatus comprising:
a control unit comprising an integrated circuit chip dedicated to an electronic money application;
a data input and output port configured to exchange monetary information via said integrated circuit chip;
a process cartridge comprising an electronic money application unit including another integrated circuit chip dedicated to said electronic money application;
a memory; and
a first communication mechanism configured to perform communications for said monetary information; and
an external host computer located at a remote control center, said external host computer comprising:
a data base for storing history information for a plurality of image recording apparatuses including said image forming apparatus; and
a second communications mechanism configured to perform communications for said monetary information,
wherein said image forming apparatus and said external host computer establish a communication connection with a specific address predetermined by said remote control center,
said image forming apparatus generates configuration information of said image forming apparatus, stores it in said memory, and sends it to said host computer through said communication connection,
said host computer generates a certified configuration information by adding a certification code to said configuration information sent from said image forming apparatus, stores it in said data base at said specific address, and sends said certified configuration information back to said image forming apparatus,
said image forming apparatus updates said configuration information with said certified configuration information received from said host computer after verification of it with said configuration information stored in said memory,
said image forming apparatus sends a request for communications for said monetary information with said certified configuration information,
said host computer approves said request for communications for said monetary information requested by said image forming apparatus by verifying said certified configuration information sent from said image forming apparatus with said certified configuration information stored in said data base.
13. An information control system as defined in claim 12, wherein said control unit generates said configuration information using said integrated circuit chips installed in said control unit and said process cartridge.
14. An information control system as defined in claim 12, wherein said host computer newly generates said certified configuration information each time it approves said request for communications requested by said image forming apparatus, said certified configuration information newly generated being different from the one previously generated, and said image forming apparatus updates said newly generated certified configuration information after said communications for said monetary information is completed.
15. An information control system as defined in claim 14, wherein said host computer controls said history information of said image forming apparatus in association with said newly generated certified configuration application and afterwards accepts said request for communications when receiving it with said newly generated certified configuration application from said image forming apparatus.
16. An information control system as defined in claim 12, wherein said history information includes apparatus history information including a cumulative number of prints performed, a cumulative amount of consumable items consumed, configuration of optional equipment, and errors that have occurred.
17. An information control system as defined in claim 12, wherein said history information includes customer history information including names of users and a cumulative number of prints performed per each user.
18. An information control method, comprising the steps of:
providing an image forming apparatus comprising:
a control unit comprising an integrated circuit chip dedicated to an electronic money application;
a data input and output port configured to exchange monetary information via said integrated circuit chip;
a process cartridge comprising an electronic money application unit including another integrated circuit chip dedicated to said electronic money application;
a memory; and
a first communication mechanism configured to perform communications for said monetary information; and
placing an external host computer located at a remote control center, said external host computer comprising:
a data base for storing history information for a plurality of image recording apparatuses including said image forming apparatus; and
a second communications mechanism configured to perform communications for said monetary information,
establishing a communication connection between said image forming apparatus and said external host computer establish with a specific address predetermined by said remote control center;
generating configuration information of said image forming apparatus;
storing said configuration information in said memory;
sending said configuration information to said host computer through said communication connection;
creating a certified configuration information by adding a certification code to said configuration information sent from said image forming apparatus;
writing said certified configuration information in said data base at said specific address;
transferring said certified configuration information back to said image forming apparatus;
updating said configuration information stored in said memory with said certified configuration information received from said host computer after verification with said configuration information stored in said memory;
transmitting a request for communications for said monetary information with said certified configuration information; and
approving said request for communications for said monetary information transmitted from said image forming apparatus by verifying said certified configuration information transferred from said image forming apparatus with said certified configuration information written in said data base.
19. An information control method as defined in claim 18, wherein said generating step generates said configuration information using said integrated circuit chips mounted in said control unit and said process cartridge.
20. An information control method as defined in claim 18, further comprising steps of newly generating said certified configuration information each time said approving step approves said request for communications transmitted from said image forming apparatus, said certified configuration information newly generated being different from the one previously generated, and updating said newly generated certified configuration information after said communications for said monetary information is completed.
21. A method of operating an item of office equipment comprising:
automatically generating and updating, at said item of office equipment, configuration and history information describing a configuration and a history thereof;
automatically storing said configuration and history information, as updated, at the item of office equipment;
removably connecting an electronic money card to said item of office equipment, and selectively charging the card in relation to at least one of said configuration and said history information stored at the item of office equipment.
22. A method as in claim 21 including the step of sending at least one of said configuration and said history information, as updated, to a remote host upon the occurrence of selected events.
23. A method as in claim 22 including the step of receiving, at said item of office equipment, an authorization code updated to reflect selected changes in at least one of said configuration and said history information, and storing the authorization code as updated.
24. A method as in claim 23 in which the step of sending at least one of said configuration and said history information, as updated, to the host comprises sending the authorization code as updated.
25. A method as in claim 24 in which the step of receiving the authorization code, as updated, comprises verifying the received code at the item of office equipment and storing the verified code for future sending to said host.
26. A method as in claim 25 in which the selected events include powering up the item of office equipment.
27. A method as in claim 25 in which the selected events include selected changes in the configuration of the item of office equipment.
28. A method as in claim 21 in which the configuration information comprises information uniquely identifying selected components of the item of office equipment.
29. A method as in claim 21 in which the history information comprises information regarding usage of the item of office equipment.
30. A method as in claim 21 including the step of carrying out image forming operations at said item of office equipment and including information thereon in said history information.
31. A method as in claim 21 comprising the step of including in said configuration information a unique identification of a consumable product included in said item of office equipment, and including in said history information data regarding replacement of said consumable product.
32. A method as in claim 31 including sending to and receiving from a host, information regarding said consumable product.
33. A method as in claim 32 including the step of charging a money card connected to the item of office equipment based at least in part on said information regarding the consumable sent to and received from the host.
34. A method of maintaining an item of office equipment communicating with a remote host comprising:
generating and updating, at said item of office equipment, at least one of configuration information describing a configuration thereof and history information describing a history thereof;
storing said configuration and history information, as updated, at the item of office equipment;
sending at least one of said configuration and said history information, as updated, to a remote host upon the occurrence of selected events, and storing at the host the information sent by the item of office equipment;
generating an authorization code at the host in response to information received from the item of office equipment, said host updating said code into an updated code in response to new information sent to the host from the item of office equipment;
wherein said storing at and sending from the item of office equipment comprises including said updated code, and wherein each of the item of office equipment and the host carries out a verification procedure to verify the updated code;
whereby matching sets of at least one of said configuration and said history information are maintained at the host and at the item of office equipment, and security is provided by the use of the updated authorization code.
35. A method as in claim 34 in which said host communicates with additional items of office equipment and maintains and updates a unique set of at least one of said configuration and said history information for each of said items of office equipment.
36. A method as in claim 35 in which at least some of said items of office equipment carry out image forming operations and include information thereof in said history information.
37. An item of office equipment comprising:
means for automatically generating and updating configuration and history information describing a configuration and a history of said item of office equipment;
means for storing said configuration and history information, as updated, at the item of office equipment;
an electronic money card removably connected to said item of office equipment; and
means for selectively charging the card in relation to at least one of said configuration and said history information stored at the item of office equipment.
38. An item of office equipment as in claim 37 including means for sending at least one of said configuration and said history information, as updated, to a remote host upon the occurrence of selected events.
39. An item of office equipment as in claim 38 including means for receiving an authorization code updated to reflect selected changes in at least one of said configuration and said history information, and storing the authorization code as updated.
40. A method as in claim 37 in which the configuration information comprises information uniquely identifying selected components of the item of office equipment.
41. A system for maintaining an item of office equipment communicating with a remote host comprising:
an item of office equipment, a remote host, and a communication link therebetween;
means for generating and updating, at said item of office equipment, at least one of configuration information describing a configuration thereof and history information describing a history thereof;
means for storing said configuration and history information, as updated, at the item of office equipment;
means for sending at least one of said configuration and said history information, as updated, to a remote host via said communication link upon the occurrence of selected events, and for storing at the host the information sent by the item of office equipment;
means for generating an authorization code at the host in response to information received from the item of office equipment, said host updating said code into an updated code in response to new information sent to the host from the item of office equipment;
wherein said storing at and sending from the item of office equipment comprises including said updated code, and wherein each of the item of office equipment and the host carries out a verification procedure to verify the updated code;
whereby matching sets of at least one of said configuration and said history information are maintained at the host and at the item of office equipment, and security is provided by the use of the updated authorization code.
42. A system as in claim 41 including additional items communicating with said host via said communication link, wherein said host maintains and updates a unique set of at least one of said configuration and said history information for each of said items of office equipment.
43. A system as in claim 42 in which at least some of said items of office equipment comprise means for carrying out image forming operations.