What is claimed is:
1. A cleaning solution comprising about 5-30% by weight of ammonium hydroxide, about 23-70% by weight of an organic solvent and about 10-50% by weight of water.
2. A cleaning solution as claimed in claim 1, wherein said ammonium hydroxide is at least one selected from the group consisting of (NH3OH)2SO4, NH3OHCl, NH3OHNO3 and (NH3OH)PO4.
3. A cleaning solution as claimed in claim 1, wherein said organic solvent is at least one selected from the group consisting of acetone, acetonitrile and MIBK (methyl isobutyl ketone).
4. A method of cleaning an organic component comprising the steps of:
coating an organic material on a semiconductor wafer installed in a predetermined equipment;
separating said equipment and then dipping said equipment into a cleaning solution comprising about 5-30% by weight of ammonium hydroxide, about 23-70% by weight of an organic solvent and about 10-50% by weight of water; and
rinsing and drying said equipment.
5. The method as claimed in claim 4, wherein said organic material is one of a photoresist and an organic ARC (anti-reflective coating) component.
6. The method as claimed in claim 4, wherein ammonium hydroxide is at least one selected from the group consisting of (NH30H)2SO4, NH3OHCl, NH3OHNO3 and (NH3OH)PO4.
7. The method as claimed in claim 4, wherein said organic solvent is at least one selected from the group consisting of acetone, acetonitrile and MIBK (methyl isobutyl ketone).
8. The method as claimed in claim 4, further comprising a step of rubbing said equipment with a wiper after completing said dipping step.
9. The method as claimed in claim 4, wherein said rinsing is implemented with acetone.
10. The method as claimed in claim 4, wherein said dipping is implemented for about 5-15 minutes.
11. The method as claimed in claim 4, wherein said equipment is a inner container installed to surround said wafer with a predetermined distance.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device formed between a wordline and a bitline, the wordline and bitline being arranged substantially orthogonal to one another, the semiconductor device comprising:
a growth layer, the growth layer comprising tantalum and having a thickness greater than about 75 Angstroms;
an antiferromagnetic layer, the antiferromagnetic layer being formed on the growth layer;
a pinned layer, the pinned layer being formed on the antiferromagnetic layer and comprising one or more pinned ferromagnetic sublayers;
a tunnel barrier layer, the tunnel barrier being formed on the pinned layer and comprising magnesium oxide; and
a free layer, the free layer being formed on the tunnel barrier layer and comprising two or more free ferromagnetic sublayers, each free ferromagnetic sublayer having a magnetic anisotropy axis that is oriented about 45 degrees from the wordline and bitline.
2. The semiconductor device of claim 1, wherein the semiconductor device comprises a magnetic tunnel junction.
3. The semiconductor device of claim 1, wherein data can be written to the semiconductor device by toggle-write operations.
4. The semiconductor device of claim 1, wherein the antiferromagnetic layer comprises iridium and manganese.
5. The semiconductor device of claim 1, wherein at least one of the pinned layer and free layer comprises iron and cobalt.
6. The semiconductor device of claim 1, wherein at least one of the pinned layer and free layer comprises boron.
7. The semiconductor device of claim 1, wherein the free layer comprises a lower free ferromagnetic sublayer formed on the tunnel barrier and an upper free ferromagnetic sublayer separated from the lower free ferromagnetic sublayer by a spacer sublayer.
8. The semiconductor device of claim 7, wherein magnetic moment vectors of the lower and upper free ferromagnetic sublayers are oriented antiparallel with respect to one another when no external magnetic field is applied to the semiconductor device.
9. The semiconductor device of claim 7, wherein the spacer sublayer comprises copper, chromium, molybdenum, ruthenium, niobium, tungsten, osmium, iridium or tantalum, or a combination thereof.
10. The semiconductor device of claim 1, wherein the pinned layer comprises a lower pinned ferromagnetic sublayer formed on the antiferromagnetic layer and an upper pinned ferromagnetic sublayer separated from the lower pinned ferromagnetic sublayer by an antiferromagnetic coupling sublayer.
11. The semiconductor device of claim 10, wherein magnetic moment vectors of the lower and upper pinned ferromagnetic sublayers are antiparallel with respect to one another.
12. The semiconductor device of claim 1, wherein the pinned layer comprises three or more pinned ferromagnetic sublayers.
13. The semiconductor device of claim 1, wherein the minimum dimension of the free layer in a plane substantially parallel to the plane incorporating an interface of the free layer and the tunnel barrier layer is less than about 200 nanometers.
14. An integrated circuit comprising at least one semiconductor device, the at least one semiconductor device being formed between a wordline and a bitline, the wordline and bitline being arranged substantially orthogonal to one another, the at least one semiconductor device comprising:
a growth layer, the growth layer comprising tantalum and having a thickness greater than about 75 Angstroms;
an antiferromagnetic layer, the antiferromagnetic layer being formed on the growth layer;
a pinned layer, the pinned layer being formed on the antiferromagnetic layer and comprising one or more pinned ferromagnetic sublayers;
a tunnel barrier layer, the tunnel barrier being formed on the pinned layer and comprising magnesium oxide; and
a free layer, the free layer being formed on the tunnel barrier layer and comprising two or more free ferromagnetic sublayers, each free ferromagnetic sublayer having a magnetic anisotropy axis that is oriented about 45 degrees from the wordline and bitline.
15. The integrated circuit of claim 14, wherein the semiconductor device comprises a magnetic tunnel junction.
16. The integrated circuit of claim 14, wherein the integrated circuit comprises magnetoresistive random access memory circuitry.
17. A method of forming a semiconductor device between a wordline and a bitline, the wordline and bitline being arranged substantially orthogonal to one another, the method comprising the steps of:
forming a growth layer, the growth layer comprising tantalum and having a thickness greater than about 75 Angstroms;
forming an antiferromagnetic layer on the growth layer;
forming a pinned layer on the antiferromagnetic layer, the pinned layer comprising one or more pinned ferromagnetic sublayers;
forming a tunnel barrier layer on the pinned layer, the tunnel barrier comprising magnesium oxide; and
forming a free layer on the tunnel barrier layer, the free layer comprising two or more free ferromagnetic sublayers, each free ferromagnetic sublayer having a magnetic anisotropy axis that is oriented about 45 degrees from the wordline and bitline.
18. The method of claim 17, wherein the step of forming the growth layer comprises physical vapor deposition.
19. The method of claim 17, wherein the step of forming at least one of the two or more free ferromagnetic sublayers comprises physical vapor deposition in the presence of an applied magnetic field.
20. The method of claim 17, wherein the step of forming the tunnel barrier comprises ion beam deposition.