1. A cold storage-based computing system, comprising:
a memory device including a target memory region;
a plurality of processors;
a shared memory controller coupled to the plurality of processors and the memory device, the shared memory controller including:
a write monitor to detect a pending write operation directed to the target memory region,
a degradation detector coupled to the write monitor, the degradation detector to determine whether the target memory region satisfies a degradation condition in response to the pending write operation; and
a cold storage migrator coupled to the degradation detector and the target memory region, the cold storage migrator to reconfigure the target memory region as a cold storage region if the target memory region satisfies the degradation condition.
2. The system of claim 1, wherein the degradation detector includes:
a write counter to update a number of write operations directed to the target memory region based on the pending write operation; and
a trigger unit to compare the number of write operations to an offset value, wherein the degradation condition is to be satisfied of the number of write operations exceeds the offset value.
3. The system of claim 1, wherein the shared memory controller further includes a cold storage reporter coupled to the cold storage migrator, the cold storage reporter to expose the cold storage region to an operating system as part of a contiguous cold storage pool.
4. The system of claim 1, wherein the cold storage migrator includes a mode adjuster to change a mode of operation for the target memory region from a volatile mode to a non-volatile mode.
5. The system of claim 1, wherein the write monitor is to detect one or more of a data processing write, a refresh write or a disturbance integrity write.
6. The system of claim 1, wherein the shared memory controller further includes a replacement memory migrator coupled to the degradation detector, the replacement memory migrator to re-map the pending write operation to a replacement memory region if the target memory region satisfies the degradation condition.
7. A method of operating a memory controller, comprising:
detecting a pending write operation directed to a target memory region;
determining whether the target memory region satisfies a degradation condition in response to the pending write operation; and
reconfiguring the target memory region as a cold storage region if the target memory region satisfies the degradation condition.
8. The method of claim 7, wherein determining whether the target memory region satisfies the degradation condition includes:
updating a number of write operations directed to the target memory region based on the pending write operation; and
comparing the number of write operations to an offset value, wherein the degradation condition is satisfied if the number of write operations exceeds the offset value.
9. The method of claim 7, further including exposing the cold storage region to an operating system as part of a contiguous cold storage pool.
10. The method of claim 7, wherein reconfiguring the target memory region includes changing a mode of operation for the target memory region from a volatile mode to a non-volatile mode.
11. The method of claim 7, wherein detecting the pending write operation includes detecting one or more of a data processing write, a refresh write or a disturbance integrity write.
12. The method of claim 7, further including re-mapping the pending write operation to a replacement memory region if the target memory region satisfies the degradation condition.
13. At least one computer readable storage medium comprising a set of instructions which, when executed by a memory controller, cause the memory controller to:
detect a pending write operation directed to a target memory region;
determine whether the target memory region satisfies a degradation condition in response to the pending write operation; and
reconfigure the target memory region as a cold storage region if the target memory region satisfies the degradation condition.
14. The at least one computer readable storage medium of claim 13, wherein the instructions, when executed, cause the memory controller to:
update a number of write operations directed to the target memory region based on the pending write operation; and
compare the number of write operations to an offset value, wherein the degradation condition is to be satisfied if the number of write operations exceeds the offset value.
15. The at least one computer readable storage medium of claim 13, wherein the instructions, when executed, cause the memory controller to expose the cold storage region to an operating system as part of a contiguous cold storage pool.
16. The at least one computer readable storage medium of claim 13, wherein the instructions, when executed, cause the memory controller to change a mode of operation for the target memory region from a volatile mode to a non-volatile mode to reconfigure the target memory region.
17. The at least one computer readable storage medium of claim 13, wherein one or more of a data processing write, a refresh write or a disturbance integrity write are detected.
18. The at least one computer readable storage medium of claim 13, wherein the instructions, when executed, cause the memory controller to re-map the pending write operation to a replacement memory region if the target memory region satisfies the degradation condition.
19. A memory controller, comprising:
a write monitor to detect a pending write operation directed to a target memory region;
a degradation detector coupled to the write monitor, the degradation detector to determine whether the target memory region satisfies a degradation condition in response to the pending write operation; and
a cold storage migrator coupled to the degradation detector and the target memory region, the cold storage migrator to reconfigure the target memory region as a cold storage region if the target memory region satisfies the degradation condition.
20. The memory controller of claim 19, wherein the degradation detector includes:
a write counter to update a number of write operations directed to the target memory region based on the pending write operation; and
a trigger unit to compare the number of write operations to an offset value, wherein the degradation condition is to be satisfied if the number of write operations exceeds the offset value.
21. The memory controller of claim 19, further including a cold storage reporter coupled to the cold storage migrator, the cold storage reporter to expose the cold storage region to an operating system as part of a contiguous cold storage pool.
22. The memory controller of claim 19, wherein the cold storage migrator includes a mode adjuster to change a mode of operation for the target memory region from a volatile mode to a non-volatile mode.
23. The memory controller of claim 19, wherein the write monitor is to detect one or more of a data processing write, a refresh write or a disturbance integrity write.
24. The memory controller of claim 19, further including a replacement memory migrator coupled to the degradation detector, the replacement memory migrator to re-map the pending write operation to a replacement memory region if the target memory region satisfies the degradation condition.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device comprising:
a memory element including a channel formation region, source and drain regions, a region for accumulating charges, and a control gate
wherein each of the source and drain regions is electrically connected to an erasing line through a semiconductor impurity region, and
wherein the source and drain regions are diode-connected to the erasing line.
2. The semiconductor device according to claim 1, wherein the memory element is provided over an insulating surface.
3. The semiconductor device according to claim 1, wherein the channel formation region, the source and drain regions, and the semiconductor impurity region are included in one semiconductor film.
4. The semiconductor device according to claim 1, wherein the source and drain regions and the semiconductor impurity region form PN junctions.
5. The semiconductor device according to claim 1, further comprising a first transistor and a second transistor,
wherein the control gate is electrically connected to a word line,
wherein one of the source and drain regions of the memory element is electrically connected to a source line through the first transistor, and
wherein the other of the source and drain regions of the memory element is electrically connected to a bit line through the second transistor.
6. The semiconductor device according to claim 1 wherein the channel formation region further comprises silicon or germanium.
7. A semiconductor device comprising:
a memory element including a channel formation region, source and drain regions, a region for accumulating charges, and a control gate
wherein:
each of the source and drain regions is electrically connected to an erasing line through a semiconductor impurity region,
a conductivity type of the source and drain regions is different from that of the semiconductor impurity region,
the source and drain regions include an impurity element at a higher concentration than the semiconductor impurity region, and
wherein the source and drain regions are diode-connected to the erasing line.
8. The semiconductor device according to claim 7, wherein the memory element is provided over an insulating surface.
9. The semiconductor device according to claim 7, wherein the channel formation region, the source and drain regions, and the semiconductor impurity region are included in one semiconductor film.
10. The semiconductor device according to claim 7, wherein the source and drain regions and the semiconductor impurity region form PN junctions.
11. The semiconductor device according to claim 7, further comprising a first transistor and a second transistor,
wherein the control gate is electrically connected to a word line,
wherein one of the source and drain regions of the memory element is electrically connected to a source line through the first transistor, and
wherein the other of the source and drain regions of the memory element is electrically connected to a bit line through the second transistor.
12. The semiconductor device according to claim 7, wherein the channel formation region further comprises silicon or germanium.
13. A semiconductor device comprising:
a memory element including a channel formation region, source and drain regions, a region for accumulating charges, and a control gate
wherein:
each of the source and drain regions is electrically connected to an erasing line through a semiconductor impurity region,
a conductivity type of the source and drain regions is different from that of the semiconductor impurity region,
the source and drain regions include an impurity element at a higher concentration than the semiconductor impurity region,
the source and drain regions are electrically connected to the semiconductor impurity region through a semiconductor region,
the source and drain regions and the semiconductor impurity region include the impurity element at a higher concentration than the semiconductor region, and
wherein the source and drain regions are diode-connected to the erasing line.
14. The semiconductor device according to claim 13, wherein the memory element is provided over an insulating surface.
15. The semiconductor device according to claim 13, wherein the channel formation region, the source and drain regions, and the semiconductor impurity region are included in one semiconductor film.
16. The semiconductor device according to claim 13, wherein the source and drain regions, the semiconductor impurity region and the semiconductor region form PIN junctions.
17. The semiconductor device according to claim 13, further comprising a first transistor and a second transistor,
wherein the control gate is electrically connected to a word line,
wherein one of the source and drain regions of the memory element is electrically connected to a source line through the first transistor, and
wherein the other of the source and drain regions of the memory element is electrically connected to a bit line through the second transistor.
18. The semiconductor device according to claim 13, wherein the channel formation region further comprises silicon or germanium.