1. A method for line speed interconnect processing, comprising:
receiving initial inputs from an input communications path;
performing a pre-sorting of the initial inputs by using a first stage interconnect parallel processor to create intermediate inputs;
performing the final combining and splitting of the intermediate inputs by using a second stage interconnect parallel processor to create resulting outputs; and
transmitting the resulting outputs out of the second stage at line speed.
2. The method of claim 1, wherein the first stage interconnect processor functions by performing a presorting and pre-clustering process on the initial inputs in parallel to identify candidates among the initial inputs to be checked for pairing.
3. The method of claim 1, wherein the second stage interconnect processor functions by performing position shuffling, pairing, and splitting of the intermediate inputs in parallel to create the resulting outputs at line speed.
4. The method of claim 1, wherein the line speed interconnect processing is implemented in a networking architecture, wherein the initial inputs comprise networking packets.
5. The method of claim 1, wherein the line speed interconnect processing is implemented in a cache accessing architecture, wherein the initial inputs comprise access requests to data of cache lines.
6. The method of claim 1, wherein the line speed interconnect processing is implemented in an arbitration architecture, wherein the initial inputs comprise streams that utilize output bandwidth, and wherein the arbitration architecture arbitrates amongst the input streams using frequency andor time multiplexing in parallel to create resulting output streams.
7. The method of claim 1, wherein the line speed interconnect processing is implemented in a computer instruction architecture decoder, wherein the initial inputs comprise computer instructions that will be combined or split in parallel into machine instructions.
8. The method of claim 1, wherein the line speed interconnect processing is implemented in a DRAM accessing architecture, wherein the initial inputs comprise accesses to DRAM pages that will be paired or split in parallel into optimized resulting accesses to DRAM pages.
9. A non-transitory computer readable memory having computer readable code which when executed by a computer system causes the computer system to implement a method for line speed interconnect processing, comprising:
receiving initial inputs from an input communications path;
performing a pre-sorting of the initial inputs by using a first stage interconnect parallel processor to create intermediate inputs;
performing the final combining and splitting of the intermediate inputs by using a second stage interconnect parallel processor to create resulting outputs; and
transmitting the resulting outputs out of the second stage at line speed.
10. The computer readable memory of claim 9, wherein the first stage interconnect processor functions by performing a presorting and pre-clustering process on the initial inputs in parallel to identify candidates among the initial inputs to be checked for pairing.
11. The computer readable memory of claim 9, wherein the second stage interconnect processor functions by performing position shuffling, pairing, and splitting of the intermediate inputs in parallel to create the resulting outputs at line speed.
12. The computer readable memory of claim 9, wherein the line speed interconnect processing is implemented in a networking architecture, wherein the initial inputs comprise networking packets.
13. The computer readable memory of claim 9, wherein the line speed interconnect processing is implemented in a cache accessing architecture, wherein the initial inputs comprise access requests to data of cache lines.
14. The computer readable memory of claim 9, wherein the line speed interconnect processing is implemented in an arbitration architecture, wherein the initial inputs comprise streams that utilize output bandwidth, and wherein the arbitration architecture arbitrates amongst the input streams using frequency andor time multiplexing in parallel to create resulting output streams.
15. The computer readable memory of claim 9, wherein the line speed interconnect processing is implemented in a computer instruction architecture decoder, wherein the initial inputs comprise computer instructions that will be combined or split in parallel into machine instructions.
16. The computer readable memory of claim 9, wherein the line speed interconnect processing is implemented in a DRAM accessing architecture, wherein the initial inputs comprise accesses to DRAM pages that will be paired or split in parallel into optimized resulting accesses to DRAM pages.
17. A computer system, comprising:
a system memory;
a central processor unit coupled to the system memory, wherein the central processor unit executes computer readable code and causes the computer system to implement a method for line speed interconnect processing, comprising:
receiving initial inputs from an input communications path;
performing a pre-sorting of the initial inputs by using a first stage interconnect parallel processor to create intermediate inputs;
performing the final combining and splitting of the intermediate inputs by using a second stage interconnect parallel processor to create resulting outputs; and
transmitting the resulting outputs out of the second stage at line speed.
18. The computer system of claim 17, wherein the first stage interconnect processor functions by performing a presorting and pre-clustering process on the initial inputs in parallel to identify candidates among the initial inputs to be checked for pairing.
19. The computer system of claim 17, wherein the second stage interconnect processor functions by performing position shuffling, pairing, and splitting of the intermediate inputs in parallel to create the resulting outputs at line speed.
20. The computer system of claim 17, wherein the line speed interconnect processing is implemented in a networking architecture, wherein the initial inputs comprise networking packets.
21. The computer system of claim 17, wherein the line speed interconnect processing is implemented in a cache accessing architecture, wherein the initial inputs comprise access requests to data of cache lines.
22. The computer system of claim 17, wherein the line speed interconnect processing is implemented in an arbitration architecture, wherein the initial inputs comprise streams that utilize output bandwidth, and wherein the arbitration architecture arbitrates amongst the input streams using frequency andor time multiplexing in parallel to create resulting output streams.
23. The computer system of claim 17, wherein the line speed interconnect processing is implemented in a computer instruction architecture decoder, wherein the initial inputs comprise computer instructions that will be combined or split in parallel into machine instructions.
24. The computer system of claim 17, wherein the line speed interconnect processing is implemented in a DRAM accessing architecture, wherein the initial inputs comprise accesses to DRAM pages that will be paired or split in parallel into optimized resulting accesses to DRAM pages.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. Siglec inhibitor with the formula:
3
whereby
X signifies a negatively charged group such as a carboxy, phosphate or sulphate group or a derivative of them;
Y signifies an H atom, an alkyl or aryl group, a hydroxy group, a glycan, a polymer carrier molecule or a derivative of them;
Z is selected from O, N, C and S;
R1 signifies an H atom, a hydroxy group or a derivative of them;
R2 signifies a hydroxy or amino group or a derivative of them;
R3 signifies a hydroxy group or a derivative of it;
R4 signifies a hydroxy group or a derivative of it;
R5 signifies a substituted or unsubstituted amino group, whereby the substituent is selected from a substituted or unsubstituted formyl, alkanoyl, cycloalkanoyl, aryl-carbonyl, heteroaryl-carbonyl, alkyl, aryl, cycloalkyl or heteroaryl group, whereby these residues can also include one or more unsaturated bonds, whereby R4 acts as H acceptor and R5 as H donor;
R6 signifies an H atom or an alkyl group, a charged group or a derivative of them;
R6 signifies an H atom or an alky group, a charged group or a derivative of them, whereby at least one substituent is selected from R6 and R6 is a hydrophobic group, preferably an H atom or a methyl group; and
R7 signifies an H atom or any group, preferably a group for improving the pharmacological properties of the siglec inhibitor.
2. Siglec inhibitor according to claim 1, whereby the alkanoyl group is selected from an ethanoyl, propanoyl, butanoyl, pentanoyl, hexanoyl, heptanoyl, octanoyl, nonanoyl and decanoyl group, preferably hexanoyl.
3. Siglec inhibitor according to claim 1, whereby the cycloalkanoyl group is selected from a C3 to C6 cycloalkanoyl group, preferably cyclohexanoyl.
4. Siglec inhibitor according to claim 1, whereby the aryl-carbonyl group is selected from a C4 to C15 aryl-carbonyl group, preferably a benzoyl group, naphthoyl group or an anthracen-carbonyl group.
5. Siglec inhibitor according to claim 1, whereby the heteroaryl-carbonyl group is selected from a pyridyl-carbonyl, chinaldine-carbonyl and thiophenyl-carbonyl group.
6. Siglec inhibitor according to claim 1, whereby the alkyl group is selected from a C1-C20 alkyl group, preferably from a methyl, ethyl, propyl, butyl, pentyl and hexyl group.
7. Siglec inhibitor according to claim 1, whereby the cycloalkyl group is selected from a C3-C6 cycloalkyl group.
8. Siglec inhibitor according to claim 1, whereby the aryl group is selected from a phenyl, naphthyl, anthracen group.
9. Siglec inhibitor according to claim 1, whereby the heteroaryl group is selected from a pyridyl and thiophenyl group.
10. Siglec inhibitor according to claim 1, whereby
X signifies a carboxy group, which should be present in an axial position;
Y signifies an H atom, an O-methyl, O-benzyl group or a derivative of a hydroxy group;
Z signifies an O atom;
R1 signifies a hydroxy group;
R2 signifies an amino-acetyl group;
R3 signifies a hydroxy group;
R4 signifies a hydroxy group;
R6 signifies an H atom;
R6 signifies an H atom; and
R7 signifies an H atom.
11. Method of increasing the binding selectivity of siglec inhibitors comprising the introduction of a substituent selected from the residues for R5 according to one of the claims 1 to 10 in position R5 of neuraminic acid or derivatives of it.
12. Method for producing siglec inhibitors with increased affinity for a siglec molecule comprising:
a) introduction of a substituent selected from the residues for R5 according to one of the claims 1 to 10 in position R5 of neuraminic acid or derivatives of it;
b) determination of the affinity of the product according to a) for a siglec molecule;
c) selection of the products with increased affinity;
d) where applicable, further substitution of the selected product according to c) in positions different from position R5, preferably in position R2.
13. Pharmaceutical composition comprising a siglec inhibitor according to one of the claims 1 to 10 and a pharmacologically compatible carrier.
14. Application of a siglec inhibitor according to one of the claims 1 to 10 in the treatment of Siglec mediated diseases.
15. Application of a siglec inhibitor according to one of the claims 1 to 10 in the regulation of the B cell dependent immune response.
16. Application of a siglec inhibitor according to claim 15 in the treatment of allergies, auto-immune diseases and chronic inflammations.
17. Application of a siglec inhibitor according to one of the claims 1 to 10 in the improvement of the regeneration capability of damaged nerves.
18. Application of a siglec inhibitor according to claim 17 in the treatment of paraplegia and multiple sclerosis.
19. Application of a siglec inhibitor according to one of the claims 1 to 10 in the regulation of the cytotoxic activity of NK cells.
20. Application of a siglec inhibitor according to claim 19 in the treatment of cancer diseases.
21. Application of a siglec inhibitor according to claim 19 in the treatment of virus diseases.
22. Application according to claim 15 for increasing the B cell response, in particular in immune-impaired patients.