1. An inkjet printhead assembly comprising:
an elongate support structure having a base and sidewalls extending from the base, the base and sidewalls having a substantially constant cross-section along the length of the elongate support structure;
a plurality of ink supply channels defined between the base and sidewalls of the elongate support structure, each supply channel for supplying a differently colored ink;
a cap secured to one terminal end of the elongate support structure and having an ink inlet port in fluid communication with at least one of the ink supply channels for communicating the respective colored ink to respective ink supply channel; and
a plurality of carrier units removably mounted to the elongate support structure, each carrier unit having a plurality of ink delivery apertures in fluid communication with an inkjet printhead segment which is mounted to the carrier unit,
wherein each carrier unit is configured to place its respective inkjet printhead segment in fluid communication with the plurality of ink supply channels of the elongate support structure via the plurality of ink delivery apertures when it is mounted to the elongate support structure.
2. An assembly according to claim 1, wherein the carrier units are removably mounted to the elongate support structure so as to extend longitudinally along the elongate support structure such that the respective inkjet printhead segments define a continuous printing zone of the inkjet printhead assembly.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of growing relaxed germanium buffer layers on a silicon substrate, the method including a step of epitaxially growing a Ge buffer layer (20) on a misoriented Si(001) substrate by low-energy plasma-enhanced chemical vapor deposition (LEPECVD), followed by a step selected from one of a group of steps consisting of thermal annealing and patterning of the epitaxially deposited layer.
2. A method of growing relaxed germanium buffer layers on a misoriented silicon substrate, the method including the steps of:
(a) cleaning the surface of a Si wafer (10) by a wet chemical treatment or a hydrogen plasma treatment;
(b) loading the Si wafer into a low-energy plasma-enhanced chemical vapor deposition (LEPECVD) reactor;
(c) increasing the temperature in the LEPECVD reactor to approximately 600\xb0 C.;
(d) epitaxially growing a Ge buffer layer (20) by LEPECVD, preferably at a rate of at least 5 nms, until a thickness of the Ge layer is reached within the range of 0.75 to 5 \u03bcm, thereby relaxing the Ge layers and reducing surface roughness measured by AFM amounts to typically 1 nm rms;
(e) raising the temperature to above 700\xb0 C., preferably to about 900\xb0 C., for about 10 minutes either in the LEPECVD reactor or in a separate annealing oven; and
(f) loading the Si wafer into another deposition chamber; and
(g) growing a layer of GaAs (30) using a vapor deposition method.
3. The method of claim 2, wherein the Ge layer (20) is covered with an oxide protection layer (25) before carrying out the annealing steps, and, wherein after the annealing steps, the oxide layer is again removed.
4. The method of claim 3, wherein the oxide protection layer (25) is a layer of silicon dioxide of a thickness of typically 100 nm.
5. The method of growing relaxed germanium buffer layers on a misoriented silicon substrate, the method including the steps of:
(a) cleaning the surface of a Si wafer (10) by a wet chemical treatment or a hydrogen plasma treatment;
(b) loading the Si wafer into a low-energy plasma-enhanced chemical vapor deposition (LEPECVD) reactor;
(c) increasing the temperature in the LEPECVD reactor to approximately 600\xb0 C.;
(d) epitaxially growing a Ge buffer layer (20) by LEPECVD, preferably at a rate of at least 5 nms, until a thickness of the Ge layer is reached within the range of 0.75 to 5 \u03bcm, thereby relaxing the Ge layers and reducing surface roughness measured by AFM amounts to typically 1 nm rms;
(e) repeatedly cycling temperature between about 700\xb0 C. and 900\xb0 C. either in the LEPECVD reactor or in a separate annealing oven, thereby annealing the heterostructure, in order to reduce the density of threading dislocations while preserving the flatness of the Ge layer; and
(f) loading the Si wafer into another deposition chamber; and
(g) growing a layer of GaAs (30) using a vapor deposition method.
6. The method of claim 5, wherein the Ge layer (20) is covered with an oxide protection layer (25) before carrying out the annealing steps and wherein, after the annealing steps, the oxide layer is again removed.
7. The method of claim 6, wherein the oxide protection layer (25) is a layer of silicon dioxide of a thickness of typically 100 nm.
8 The method of one of claims 2 and 5, wherein the GaAs layer (30) of step (g) is composed of different layers, for example with different doping types and levels, in order to be useful for solar cell or lasers structures.
9. The method of one of claims 2 and 5, wherein layer (30) is composed of several sub-layers which are doped differently.
10. The method of claim 9, wherein layer (30) contains quantum well layers or quantum dot layers, as are known to be useful for microelectronic and optoelectronic applications, or an active region of high-efficiency solar cells; or an active region of quantum well and quantum dot lasers, or an active regions of modulation-doped field effect transistors.
11. The method of growing relaxed germanium buffer layers on a misoriented silicon substrate, the method including the steps of:
(a) cleaning the surface of a Si wafer by a wet chemical treatment or a hydrogen plasma treatment;
(b) loading the Si wafer into a low-energy plasma-enhanced chemical vapor deposition (LEPECVD) reactor;
(c) increasing the temperature in the LEPECVD reactor to approximately 600\xb0 C.;
(d) epitaxially growing a Si buffer layer (12) by LEPECVD;
(e) epitaxially growing a Ge buffer layer (20) by LEPECVD, preferably at a rate of at least 5 nms, until a thickness of the Ge layer is reached within the range of 0.75 to 5 \u03bcm, thereby relaxing the Ge layers and reducing surface roughness measured by AFM amounts to typically 1 nm rms; and
(f) annealing the heterostructure by raising the temperature to above 700\xb0 C., preferably to about 900\xb0 C. either in the LEPECVD reactor or in a separate annealing oven, for about 10 minutes.
(g) loading the Si wafer into another deposition chamber; and
(h) growing a layer of GaAs (30) using a vapor deposition method.
12. The method of growing relaxed germanium buffer layers on a misoriented silicon substrate, the method including the steps of:
(a) cleaning the surface of a Si wafer by a wet chemical treatment or a hydrogen plasma treatment;
(b) loading the Si wafer into a low-energy plasma-enhanced chemical vapor deposition (LEPECVD) reactor;
(c) increasing the temperature in the LEPECVD reactor to approximately 600\xb0 C.;
(d) epitaxially growing a Si buffer layer (12) by LEPECVD;
(e) epitaxially growing a Ge buffer layer (20) by LEPECVD, preferably at a rate of at least 5 nms, until a thickness of the Ge layer is reached within the range of 0.75 to 5 \u03bcm, thereby relaxing the Ge layers and reducing surface roughness measured by AFM amounts to typically 1 nm rms; and
(f) repeatedly cycling temperature between about 700\xb0 C. and 900\xb0 C. either in the LEPECVD reactor or in a separate annealing oven, thereby annealing the heterostructure, in order to reduce the density of threading dislocations while preserving the flatness of the Ge layer; and
(g) loading the Si wafer into another deposition chamber; and
(h) growing a layer of GaAs (30) using a vapor deposition method.
13. The method of one of claims 11 and 12, wherein the Ge layer (20) is covered with an oxide protection layer (25) before carrying out the annealing steps, and wherein, after the annealing steps, the oxide layer is again removed.
14. The method of claims 12 and 13, wherein the oxide protection layer (25) is a layer of silicon dioxide of a thickness of typically 100 nm.
15. The method of one of claims 11 and 12, wherein the Si buffer layer (12) is grown at lower rate than the Ge layer, for example below 1 nms.
16. The method of one of claims 2, 5, 11 and 12, wherein a GaAs interlayer (32) is introduced before layer (30) is grown, thereby helping to reduce the number of threading dislocations that penetrate from the Ge buffer layer (20) into the GaAs layer (30).
17. The method of claim 16, wherein the interlayer (32) is grown by atomic-layer epitaxy (ALE), where Ga and As are supplied sequentially, resulting in a GaAs superlattice.
18. The method of one of claims 2, 5, 11 and 12 wherein the Ge layer (20) is patterned prior to growing layers (30) and (32).
19. The method of claim 18 wherein the patterning is made by a square array of grooves or in parallel grooves having a spacing of approximately 10 to 20 \u03bcm.
20. The method of claim 19, wherein the depth of the grooves is less than the thickness of layer (20).
21. The method of one of claims 19, 20, wherein the grooves are preferably 1 to 2 micrometer wide.
22. The method of claim 18, wherein the patterning is composed of grooves defined by photolithography, followed by reactive ion etching, wherein a polymer acts as an etch mask.
23. The method of claim 18, wherein the patterning is composed of grooves defined by photolithography, followed by wet-chemical etching.
24. The method of claim 18, wherein the patterning is composed of grooves defined by a mask suitable for a subsequent wet-chemical etching step may be formed by a printing process, where a polymer resistant to the etching solution is applied by a stamp.
25. The method of claim 18, wherein the patterning includes features in which feature size does not exceed a critical size of the order of 10-20 \u03bcm, and wherein spacing between features is on the order of a few micrometers, in order to produce a pattern resulting in reduction of threading dislocation densities.
26. The method of claim 18, wherein after the patterning of layer (20), an annealing step to temperatures above 700\xb0 C. is carried out, preferably up to approximately 900\xb0 C. in order to induce movement of the threading dislocations into the grooves.
27. The method of claim 18, wherein the annealing step is repeated by temperature cycling, preferably between 700\xb0 C. and 900\xb0 C. in order to induce movement of the threading dislocations into the grooves.
28. The method of one of claims 2, 5, 11 and 12, wherein layer (30) comprises a layer of GaAs to which a small amount of In has been added, wherein the In concentration is kept low, preferably on the order of 1 percent, resulting in a compressive strain of layer (30) at the substrate temperature used for MBE or MOCVD growth.
29. A IIIV semiconductor made according to any of the above methods, wherein the epitaxial growth method used is LEPECVD.
30. The semiconductor of claim 29, wherein to grow a GaAs layer (30), a Ga-containing reactive gas, such as trimethyl-gallium, is introduced into the LEPECVD deposition chamber simultaneously to an As-containing gas such as arsine (AsH3) in order to attain epitaxial growth rates above 2 nms when the plasma is sufficiently dense.
31. A semiconductor product made from any of the above methods.