1. An alarm unit, comprising:
a flash circuit having a flashtube for generating a flash; and
an application specific integrated circuit (ASIC) coupled to the flash circuit, for triggering the flash, wherein the ASIC controls an energy level of the flashtube via a sense resistor in a current sensing circuit coupled to the ASIC.
2. The alarm unit of claim 1, further comprising:
a switch, coupled to said ASIC, where said switch having a plurality of selectable positions representative of a plurality of intensity settings, wherein said flash has an intensity that is in accordance with a selected position of said switch.
3. The alarm unit of claim 2, wherein said plurality of intensity settings comprise four intensity settings.
4. The alarm unit of claim 1, further comprising:
a current limiting circuit, coupled to said ASIC, where said current limiting circuit limits an input current level when the input current level rises above a set level.
5. The alarm unit of claim 4, wherein said current limiting circuit continuously senses said input current level.
6. The alarm unit of claim 4, wherein the set level is determined by a voltage level on a resistor of the current limiting circuit of the ASIC.
7. The alarm unit of claim 6, wherein the set level is changed by changing the sense resistor.
8. The alarm unit of claim 1, further comprising:
a DC to DC converter, coupled to said ASIC, where said DC to DC boost converter provides over voltage protection.
9. The alarm unit of claim 1, wherein said ASIC is deployed in an eighteen-pin package.
10. The alarm unit of claim 1, wherein said ASIC is deployed in a sixteen-pin package.
11. The alarm unit of claim 1, wherein said ASIC is deployed in an eight-pin package.
12. The alarm unit of claim 1, wherein said flash circuit further comprises a voltage doubler.
13. The alarm unit of claim 1, wherein said ASIC provides a charge cycle that is greater than 8 kilohertz.
14. The alarm unit of claim 1, further comprising:
an audio circuit, coupled to said ASIC, where said audio circuit generates an audio warning signal.
15. The alarm unit of claim 11, wherein said ASIC selects an audio frequency for said audio warning signal.
16. The alarm unit of claim 1, further comprising:
a synchronization detection circuit, coupled to said ASIC, where said synchronization detection circuit receives a synchronization signal to trigger said flash.
17. The alarm unit of claim 1, wherein said ASIC provides a transistor drive capability of greater than 7.3 volts.
18. The alarm unit of claim 1, wherein the flashtube requires approximately 125-250 volts to fire.
19. The alarm unit of claim 1, wherein the sense resistor goes to a pin of the ASIC that monitors and controls the energy level of the flashtube.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for fabricating a semiconductor device, comprising:
providing a first wafer having a first active surface and a first rear surface opposite to the first active surface, the first wafer comprising a first circuit formed therein; wherein the first wafer comprises:
a first semiconductor substrate comprising a plurality of first components therein; and
a first interconnection layer on the first semiconductor substrate, wherein the first interconnection layer is electrically connected to the first components,
providing a second wafer having a second active surface and a second rear surface opposite to the second active surface, the second wafer comprising a second circuit formed therein; wherein the second wafer comprises:
a second semiconductor substrate comprising a plurality of second components therein; and
a second interconnection layer on the second semiconductor substrate, wherein the second interconnection layer is electrically connected to the second components,
bonding the first active surface of the first wafer with the second active surface of the second wafer so as to electrically connecting the first circuit and the second circuit;
thinning the second wafer from the second rear surface; and
forming at least a conductive through via in the second wafer, wherein the conductive through via is electrically connected to the first circuit through the second circuit,
wherein forming the at least a conductive through via in the second wafer comprises:
forming a first side wall portion in the second semiconductor substrate under a first etching condition; wherein the first side wall portion is connected to the second interconnection layer on the second semiconductor substrate, and the first side wall portion comprises a plurality of first scallops;
forming a second wall portion in the second semiconductor substrate under a second etching condition; wherein the second side wall portion is connected to the second rear surface of the second semiconductor substrate, the first side wall portion and the second side wall portion form a through hole; and
forming a conductive post in the through hole to form the conductive through via, wherein the conductive post and the second interconnection layer are electrically connected.
2. The method for fabricating a semiconductor device of claim 1, wherein the first wafer comprises a silicon-on-insulator (SOI) wafer.
3. The method for fabricating a semiconductor device of claim 1, wherein a portion of the second semiconductor substrate is removed when thinning the second wafer from the second rear surface.
4. The method for fabricating a semiconductor device of claim 1, wherein the second wafer comprises:
a detach interface in the second semiconductor substrate, the second components being located at one side of the detach interface.
5. The method for fabricating a semiconductor device of claim 4, wherein a portion of the second semiconductor substrate is detached from the detach interface when thinning the second wafer from the second rear surface.
6. The method for fabricating a semiconductor device of claim 1, wherein the second wafer comprises a silicon-on-insulator (SOI) wafer.
7. The method for fabricating a semiconductor device of claim 6, wherein a portion of the second semiconductor substrate is removed until an insulator of the SOI wafer is exposed when thinning the second wafer from the second rear surface.
8. The method for fabricating a semiconductor device of claim 1, wherein the second semiconductor substrate of the second wafer comprises:
a plurality of isolation structures and a plurality of second components disposed therein, wherein the isolation structures define a plurality of active regions, and the second components are formed in the active regions.
9. The method for fabricating a semiconductor device of claim 8, wherein the conductive through via penatrates one of the isolation structures.
10. The method for fabricating a semiconductor device of claim 8, wherein the through hole penatrates one of the active regions.
11. The method for fabricating a semiconductor device of claim 1 further comprising:
forming a re-distribution wiring layer over the second semiconductor substrate after the conductive through via is formed, wherein the re-distribution wiring layer is electrically connected to the conductive through via.
12. The method for fabricating a semiconductor device of claim 1, wherein the second side wall portion comprises a non-scalloped surface, and an included angle is formed between the non-scalloped surface and the second surface.