1. A semiconductor structure, comprising:
a substrate comprising an active region and an isolation region;
a gate structure having a portion disposed above the active region and a portion disposed above the isolation region of the substrate;
source and drain regions disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region; and
a gate contact structure disposed on the portion of the gate structure disposed above the active region of the substrate.
2. The semiconductor structure of claim 1, wherein the gate contact structure is a self-aligned via.
3. The semiconductor structure of claim 1, wherein the active region of the substrate is a three-dimensional semiconductor body.
4. The semiconductor structure of claim 3, wherein the substrate is a bulk silicon substrate.
5. A semiconductor structure, comprising:
a substrate comprising an active region and an isolation region;
a plurality of gate structures, each having a portion disposed above the active region and a portion disposed above the isolation region of the substrate;
a plurality of source or drain regions disposed in the active region of the substrate, between the portions of the gate structures disposed above the active region;
a plurality of trench contacts, a trench contact disposed on each of the source or drain regions;
a gate contact via disposed on one of the gate structures, on the portion of the gate structure disposed above the active region of the substrate; and
a trench contact via disposed on one of the trench contacts.
6. The semiconductor structure of claim 5, wherein the gate contact via and the trench contact via are disposed essentially co-planar in a same inter-layer dielectric layer disposed above the substrate.
7. The semiconductor structure of claim 6, wherein the inter-layer dielectric layer is a bi-layer structure comprising a top low-k dielectric layer and a bottom etch selectivity layer.
8. The semiconductor structure of claim 5, wherein the gate contact via and the trench contact via are substantially co-planar with one another.
9. The semiconductor structure of claim 5, wherein each of the gate structures further comprises a pair of sidewall spacers, and wherein the trench contacts are disposed directly adjacent to the sidewall spacers of a corresponding gate structure.
10. The semiconductor structure of claim 9, wherein a top surface of the plurality of gate structures is substantially co-planar with a top surface of the plurality of trench contacts.
11. The semiconductor structure of claim 10, wherein the top surface of the plurality of gate structures and the top surface of the plurality of trench contacts are below a top surface of each of the pair of sidewall spacers.
12. The semiconductor structure of claim 11, wherein each of the plurality of gate structures comprises a gate cap dielectric layer, or remnant thereof, on the top surface of the gate structure and substantially co-planar with the corresponding pair of sidewall spacers.
13. The semiconductor structure of claim 12, wherein each of the plurality of trench contacts comprises a trench cap dielectric layer, or remnant thereof, on the top surface of the trench contact and substantially co-planar with the corresponding pair of sidewall spacers.
14. The semiconductor structure of claim 13, wherein the gate cap dielectric layer and the trench cap dielectric layer have different etch selectivities relative to one another.
15. The semiconductor structure of claim 9, wherein a top surface of the plurality of gate structures is approximately co-planar with a top surface of each of the pair of sidewall spacers.
16. The semiconductor structure of claim 5, wherein the gate contact via is further disposed on a second of the gate structures, on the portion of the second gate structure disposed above the active region of the substrate, wherein the gate contact via couples the one and the second gate structures.
17. The semiconductor structure of claim 5, wherein the trench contact via is further disposed on a second of the trench contacts and couples the one and the second trench contacts.
18. The semiconductor structure of claim 5, wherein the gate contact via is a self-aligned via, and the trench contact via is a self-aligned via.
19. The semiconductor structure of claim 5, wherein the active region of the substrate is a three-dimensional semiconductor body.
20. The semiconductor structure of claim 19, wherein the substrate is a bulk silicon substrate.
21. The semiconductor structure of claim 5, wherein the gate structures comprise a high-k gate dielectric layer and a metal gate electrode.
22. A method of fabricating a semiconductor structure, the method comprising:
forming a plurality of gate structures above an active region of a substrate;
forming a plurality of source or drain regions in the active region of the substrate, between the gate structures;
forming a plurality of trench contacts, a trench contact formed on each of the source or drain regions;
forming a gate cap dielectric layer above each of the gate structures;
forming a trench cap dielectric layer above each of the trench contacts;
forming a gate contact via on one of the gate structures, the forming comprising etching the corresponding gate cap dielectric layer selective to a trench cap dielectric layer; and
forming a trench contact via on one of the trench contacts, the forming comprising etching the corresponding trench cap dielectric layer selective to a gate cap dielectric layer.
23. The method of claim 22, wherein forming the gate contact via and the trench contact via comprises forming conductive material for both in a same process operation.
24. The method of claim 22, wherein forming the plurality of gate structures comprises replacing dummy gate structures with permanent gate structures.
25. The method of claim 22, wherein forming the plurality of trench contacts comprises replacing dummy gate trench contact structures with permanent trench contact structures.
26. The method of claim 22, further comprising:
prior to forming the plurality of gate structures, forming a three-dimensional body from the active regions of the substrate.
27. The method of claim 26, wherein forming the three-dimensional body comprises etching fins in a bulk semiconductor substrate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed:
1. A process for manufacturing a multicolor electrophoretic display, comprising the steps of:
a) filling display cells with a filler material;
b) selectively opening filled cells and removing the filler material from the opened cells;
c) filling said opened cells with a display fluid and a dispersion of a sealing material which has a specific gravity lower than that of the display fluid;
d) sealing said opened and filled cells of (c) by hardening the dispersion of the sealing material during or after it phase separates and forms a supernatant layer above the display fluid; and
e) repeating the above a) through d) processing steps sequentially with one or more different color display fluids until the multicolor display is formed.
2. The process of claim 1 wherein said filling is carried out by screen printing, gravure printing or inkjet printing.
3. The process of claim 2 wherein said filling is carried out by inkjet printing.
4. The process of claim 1 wherein step (b) is carried out by coating said filled cells with a layer of photoresist, followed by imagewise exposing and developing the exposed photoresist.
5. The process of claim 1 wherein said filler material is capable of being readily removed from the cells by using a cleaning solution which is a weak solvent or non-solvent for a non-exposed photoresist, but is a good solvent or dispersion medium for the filler material.
6. The process of claim 5 wherein said cleaning solution is an aqueous solution.
7. The process of claim 1 wherein said filler material is selected from the group consisting of organic particulates, inorganic particulates, polymer particulates, water soluble and dispersible polymers, and mixtures thereof.
8. The process of claim 7 wherein said filler material is selected from the group consisting of water-dispersible branched sulfopolyesters, carboxylated acrylic-based polymers, poly(vinyl alcohol), polyvinylpyrrolidone, poly(4-vinyl phenol), pre-exposed positive photoresists, polyacrylic acid, polymethacrylic acid, and their copolymers, zinc ionomer of ethylene copolymer, sodium ionomer dispersion of ethylene acrylic acid copolymer, and N,N-diethylethanolamine dispersions, non-film forming latexes, colloidal silica and mixtures thereof.
9. The process of claim 1 wherein said filler material comprises an additive selected from the group consisting of surfactants, dispersing agents and photosensitive dissolution-inhibiting compounds.
10. The process of claim 9 wherein said photosensitive dissolution-inhibiting compound is a diazide compound.
11. The process of claim 1 wherein said filler material is a pre-exposed positive working novolac photoresist.
12. The process of claim 4 wherein said photoresist comprises a layer with a thickness in the range of about 0.5 to 15 microns.
13. The process of claim 12 wherein said photoresist comprises a layer with a thickness in the range of about 1 to 3 microns.
14. The process of claim 11 wherein said photoresist is selected from the group consisting of the novolac-based photoresist S-1818, SJR-1075, SJR-3000, SJR-5440, SJR-5740, AZ-9260, AZ-4620, AZ-4562, THB-Positive and mixtures thereof.
15. The process of claim 4 wherein said photoresist is a polyvinylphenol-based photoresist.
16. The process of claim 4 wherein said photoresist is a t-BOC derivative of a polyvinylphenol-based photoresist.
17. The process of claim 4 wherein said exposing step is performed by radiation with UV, visible light or other radiation sources.
18. The process of claim 17 further comprising a step of soft baking the photoresist before said exposing step.
19. The process of claim 4 wherein said developing step comprises contacting said exposed cells with a developing solution.
20. The process of claim 19 wherein said developing solution is a base developer selected from the group consisting of alkaline solutions, sodium hydroxide, sodium tetraborate decahydrate and borate solution and potassium hydroxide and borate solution.
21. The process of claim 19 wherein said developing solution comprises an additive.
22. The process of claim 21 wherein said additive is a surfactant or dispersing agent.
23. The process of claim 4 wherein the developing step further comprising a step of washing the developed cells with a solvent or a mixture of solvents.
24. The process of claim 23 wherein the solvent is distilled water or deionized water.
25. The process of claim 1 wherein said display fluid is an electrophoretic fluid comprising a dispersion of particles in a colored dielectric solvent.
26. The process of claim 25 wherein said particles are white particles.
27. The process of claim 1 wherein said display fluid is liquid crystals.
28. The process of claim 27 wherein said liquid crystals comprise a dichroic dye.
29. The process of claim 1 wherein said display fluid colors are red, blue and green in no particular order.
30. The process of claim 1 wherein said sealing material is a thermoplastic or thermoset precursor composition.
31. The process of claim 30 wherein said hardening of said thermoplastic or thermoset precursor composition is accomplished by evaporation of a solvent or plasticizer, by cooling, interfacial reaction, moisture, heat, radiation or a combination of the above-mentioned methods.
32. The process of claim 1 wherein the steps are performed in a roll-to-roll processing technology, conveyed in continuous or semi-continuous operation.
33. The process of claim 8 wherein said non-film forming latex is PMMA or polystyrene latex.
34. A multicolor electrophoretic display manufactured according to the process of claim 1 wherein the optically active viewing fraction of surface area of said display is greater than about 40%.