1460707552-66ce6cf5-7b8a-4ad6-b0c1-ee3db7a7f24d

What is claimed is:

1. An amplifier circuit comprising:
a first circuit branch, coupled between a first node and a second node, comprising a first impedance matching unit and a power stage unit, coupled in series; and
a second circuit branch, coupled between the first node and the second node, comprising an impedance transformer unit,
wherein during a first mode of operation of the amplifier circuit, a signal path passes substantially through the first circuit branch, and during a second mode of operation of the amplifier circuit, the signal path passes substantially through the second circuit branch,
and during the first mode and second mode, the impedance transformer unit is coupled in parallel to the first circuit branch and the signal path through the second circuit branch does not pass through a switch device.
2. The amplifier circuit of claim 1 wherein the first circuit branch further comprises a second impedance matching unit coupled in series with the first impedance matching unit and the power stage unit.
3. The amplifier circuit of claim 1 further comprising:
a control circuit providing a control signal coupled to the power stage unit to place the power stage unit in a first state during the first mode and a second state during the second mode.
4. The amplifier circuit of claim 1 wherein during the first mode, the power stage unit provides a high impedance, and during the second mode, the power stage unit provides gain.
5. The amplifier circuit of claim 1 wherein during the first mode, the power stage unit consumes less power than during the second mode.
6. The amplifier circuit of claim 1 wherein the switch device may include any of a relay, micromachined switch, transistor switch, PIN diode switch, or Schottky diode switch.
7. The amplifier circuit of claim 1 wherein the first branch does not include any of a relay, micromachined switch, transistor switch, PIN diode switch, or Schottky diode switch.
8. The amplifier circuit of claim 1 wherein an impedance level at an input of the impedance transformer unit is determined by a combination of at least the first impedance unit and the impedance transformer unit.
9. The amplifier circuit of claim 1 wherein the signal path through the first branch does not pass through a switch device.
10. A wireless transceiver device comprising the amplifier circuit as recited in claim 1.
11. An amplifier circuit comprising:
a first impedance matching unit;
a fourth impedance matching unit;
a first circuit branch, coupled between the first and fourth impedance matching units, comprising:
a second impedance matching unit, a power stage unit, and a third impedance matching unit, coupled in series; and

a second circuit branch, coupled between the first and fourth impedance matching units, comprising an impedance transformer unit,
wherein in a first mode of the amplifier, the power stage unit is placed in a first state and in a second mode of the amplifier, the power stage unit is placed in a second state, and when the power stage unit is in the second state, an impedance level at an input to the impedance transformer, as viewed from the first impedance matching unit, is greater than an impedance level at an input to the second impedance matching unit.
31. The amplifier circuit of claim 30 wherein when the power stage is in the second state, an impedance level at the second branch is at least about two times an impedance level at the first branch.
32. A multiple power mode amplifier configured for use in a portable electronic device, the amplifier comprising:
a driver to provide a power signal;
a power stage transistor including an input node and an output node, the input node of the power stage transistor being coupled to the driver to receive the power signal from the driver in a high power mode;
an impedance transformer including an input node and an output node and provided in a parallel branch to the power stage transistor, the input node of the impedance transformer being configured to receive the power signal from the driver in a low power mode; and
a control circuit coupled to the power stage transistor and configured to apply a first control signal to the power stage transistor to place the power stage transistor in an off-state during the low power mode and a second control signal to the power stage transistor to place the power stage transistor in an on-state during the high power mode,
wherein in the off-state, the power stage transistor directs the power signal from the driver primarily to a bypass path including the impedance transformer, and in the on-state, the power stage transistor directs the power signal from the driver primarily to a power stage path including the power stage transistor.
33. The amplifier of claim 32 wherein the power stage transistor includes a plurality of transistors configured to amplify the power signal received from the driver if the power stage transistor receives the second control signal from the voltage control circuit.
34. The amplifier of claim 32 further comprising:
a first impedance matching unit provided between the driver and the power stage transistor;
a second impedance matching unit provided between the first impedance matching unit and the power stage transistor; and
a third impedance matching unit having a first side and a second side, the first side of the third impedance matching unit being coupled to the output node of the power stage transistor, the second side of the third impedance matching unit being coupled to the output node of the impedance transformer; and a fourth impedance matching unit being coupled to the second side of the third impedance matching unit and the output node of the impedance transformer.
35. The amplifier of claim 34 wherein the impedance transformer is configured to cooperate with the third and fourth impedance matching units to provide a first impedance level at the input of the impedance transformer, as viewed from the first impedance matching unit, during the low power mode and a second impedance level at the input of the impedance transformer, as viewed from the first impedance matching unit, during the high power mode, the first impedance level at the input of the impedance transformer being less than the second impedance level at the input of the impedance transformer.
36. The amplifier of claim 34 wherein the impedance transformer is configured to cooperate with the third and fourth impedance matching units to increase an input impedance of the bypass path to be higher than that of the power stage path during the high power mode, the bypass path being defined by the impedance transformer, the power stage path being defined by the second impedance matching unit, and the power stage transistor, and the third impedance matching unit.
37. The amplifier of claim 34 wherein the second impedance matching unit is configured to provide an increased impedance level as viewed from the first impedance matching unit during the low power mode.
38. The amplifier of claim 37 wherein the second impedance matching unit provides inter-stage matching during the high power mode.
39. The amplifier of claim 32 further comprising:
an impedance matching unit provided between the driver and the power stage transistor; and
another impedance matching unit being coupled to the output node of the impedance transformer and an output stage.
40. A portable electronic device comprising:
a power source; and
a power amplifier coupled to the power source, the power amplifier comprising
a driver to provide a power signal;
a power stage transistor including an input node and an output node, the input node of the power stage transistor being coupled to the driver to receive the power signal from the driver in a high power mode; and
an impedance transformer including an input node and an output node and provided in a parallel branch to the power stage transistor, the input node of the impedance transformer being configured to receive the power signal from the driver in a low power mode; and
a control circuit coupled to the power stage transistor and configured to apply a first control signal to the power stage transistor to place the power stage transistor in an off-state during the low power mode and a second control signal to the power stage transistor to place the power stage transistor in an on-state during the high power mode,

wherein the off-state of the power stage transistor directs the power signal from the driver primarily to a bypass path including the impedance transformer and the on-state of the power stage transistor directs the power signal from the driver primarily to a power stage path including the power stage transistor.
41. The portable electronic device of claim 40 wherein the portable device is a mobile phone, cell phone, or personal digital assistant.
42. A multiple power mode amplifier configured for use in a mobile phone, the amplifier comprising:
a driver to provide a power signal;
a power stage transistor including an input node and an output node, the input node of the power stage transistor being coupled to the driver and being configured to receive the power signal from the driver during a high power mode operation;
a first impedance matching unit coupled to the driver to receive the power signal output by the driver;
a second impedance matching unit provided between the first impedance matching unit and the power stage transistor;
an impedance transformer including an input node and an output node and provided in a parallel branch to the power stage transistor, the input node of the impedance transformer being configured to receive the power signal from the first impedance matching unit during a low power mode operation;
a third impedance matching unit having a first side and a second side, the first side of the third impedance matching unit being coupled to the output node of the power stage transistor; and
a fourth impedance matching unit being coupled to the second side of the third impedance matching unit and the output node of the impedance transformer.
43. The amplifier of claim 42 wherein the driver is a variable gain amplifier.
44. The amplifier of claim 42 further comprising:
an applied voltage control circuit coupled to the power stage transistor and being configured to provide a high power mode signal to turn on the power stage transistor and a low power mode signal to turn off the power stage transistor.
45. A multiple power mode power amplifier comprising:
a power stage transistor circuit configured to receive a first power signal from a driver via first and second impedance matching units during a high power mode and output a second power signal that has greater power than the first power signal;
a control circuit coupled to the power stage transistor circuit and configured to apply a first control signal to the power stage transistor circuit during the high power mode to turn on the power stage transistor and apply a second control signal to the power stage transistor during a low power mode to turn off the power stage transistor;
an impedance transformer configured to receive a third power signal from the driver via the first impedance matching unit during the low power mode, the third power signal having less power than the second power signal;
a third impedance matching unit coupled to the power stage transistor circuit in series and configured to receive the second power signal output by the power stage transistor during the high power mode; and
a fourth impedance matching unit coupled to the third impedance matching unit and configured to receive the second power signal from the third impedance matching unit or the third power signal from the impedance transformer and transfer the received second or third power signal to an output stage.
46. The multiple power mode power amplifier of claim 45 wherein the impedance transformer is connected in a parallel branch to the second impedance matching unit, the power stage transistor, and the third impedance matching unit.
47. The multiple power mode power amplifier of claim 45 wherein the third impedance matching unit prevents power transferred through the impedance transformer from leaking to the power stage transistor during the low power mode.
48. The multiple power mode power amplifier of claim 45 wherein the driver is a variable gain amplifier.
49. The multiple power mode power amplifier of claim 48 wherein the control circuit controls the driver in order for gain of a signal inputted into the driver to be differently amplified according to the high and low power modes.
50. The multiple power mode amplifier of claim 45 wherein the power stage transistor includes a plurality of transistors.
51. The multiple power mode amplifier of claim 45 wherein the amplifier is configured to be used in a mobile telephone, cell phone, or personal digital assistant.
52. A method of operating an amplifier circuit comprising:
providing a second impedance matching unit;
providing a power stage circuit having an input coupled to the second impedance matching unit, wherein the power stage has a control input;
providing a third impedance matching unit coupled to an output of the power stage;
providing an impedance transformer unit coupled to the second and third impedance matching unit; and
providing a fourth impedance matching unit coupled to the third impedance matching unit.
53. The method of claim 52 further comprising:
providing a control signal to the control input of the power stage to place the amplifier circuit in a first mode, when in the first mode, a signal path substantially passes through the impedance transformer and fourth impedance matching unit instead of through the second impedance matching unit, power stage, and third impedance matching unit.
54. The method of claim 52 further comprising:
providing a control signal to the control input of the power stage to place the amplified circuit in a second mode, where in the second mode, a signal path substantially passes through the second impedance matching unit, power stage, third impedance matching unit, and fourth impedance matching unit instead of through the impedance transformer.
55. The method of claim 53 wherein a signal for transmission on the signal path is an AC signal.
56. The method of claim 52 further comprising:
providing a first impedance matching unit coupled to the second impedance matching unit.
57. The method of claim 53 wherein the first mode, the second impedance matching unit has a relatively high impedance at its input compared to an impedance at an input of the impedance transformer.
58. The method of claim 53 wherein in the first mode, the third impedance unit has a relatively high impedance at its output compared to an impedance at an input of the fourth impedance matching unit.
59. The method of claim 54 wherein in the second mode, the second impedance matching unit has a relatively low impedance at its input compared to an impedance at an input of the impedance transformer.
60. The method of claim 54 wherein in the second mode, the impedance transformer unit has a relatively high impedance at its output compared to an impedance at an input of the fourth impedance matching unit.
61. The method of claim 52 wherein the impedance transformer is coupled to the second impedance matching unit without passing through a switch circuit.
62. The method of claim 52 wherein the second impedance matching unit is coupled to the first impedance matching unit without passing through a switch circuit.
63. The method of claim 52 wherein the impedance transformer is coupled to the fourth impedance matching unit without passing through a switch circuit.
64. The method of claim 52 wherein the third impedance matching unit is coupled to the fourth impedance matching unit without passing through a switch circuit.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1. A system for automatic pipeline composition, wherein the system comprises:
a processor, wherein the processor executes code; and
a code store, wherein syntax elements are injected into a code within the code store, wherein the syntax elements specify independent functions to be coalesced into a single loop, and data accesses to be coalesced for each function.
2. The system of claim 1, wherein a compiler uses compiler flags to inject syntax elements into the code.
3. The system of claim 1, wherein a user explicitly inserts syntax elements into the code.
4. The system of claim 1, wherein injecting syntax elements comprises automatically inferring the syntax elements using static code analysis.
5. The system of claim 1, wherein injecting syntax elements comprises explicitly indicating the syntax elements using pragmas or special data types.
6. The system of claim 1, wherein the syntax elements are data attributes that describe the organization of the data.
7. The system of claim 1, wherein the syntax elements are compute attributes that describe the data types, functions, and buffer sizes to be coalesced.
8. The system of claim 1, wherein the processor injects syntax elements into the code using native language of the processor prior to the execution of the code.
9. The system of claim 1, wherein a compiler injects syntax elements into the code at an intermediate level, wherein the intermediate level is based on an abstraction of a hardware of the system.
10. The system of claim 1, wherein the syntax elements are injected into high level programming languages or the syntax elements are injected by a compiler or a translator.
11. The system of claim 1, where a run time system generates optimized machine code using syntax elements which executes on a target processor.
12. An apparatus for automatic pipeline composition, comprising:
logic to inject syntax elements into a code, wherein the syntax elements specify independent functions to be coalesced into a single loop, and data accesses to be coalesced for each function;
logic to execute the pipeline, wherein the pipeline comprises the coalesced functions and data accesses.
13. The apparatus of claim 12, wherein the logic to inject syntax elements comprises automatically inferring the syntax elements using compiler flags.
14. The apparatus of claim 12, wherein the logic to inject syntax elements comprises automatically inferring the syntax elements using static code analysis.
15. The apparatus of claim 12, wherein the logic to inject syntax elements comprises explicitly indicating the syntax elements using pragmas or special data types.
16. The apparatus of claim 12, wherein the syntax elements are data attributes that describe the organization of the data.
17. The apparatus of claim 12, wherein the syntax elements are compute attributes that describe the data types, functions, and buffer sizes to be coalesced.
18. The apparatus of claim 12, further comprising a run time system to generate optimized machine code using syntax elements which execute on a target processor.
19. The apparatus of claim 12, wherein the apparatus is a printing device.
20. The apparatus of claim 12, wherein the apparatus is an image capture mechanism.
21. At least one machine readable medium having instructions stored therein that, in response to being executed on a computing device, cause the computing device to:
inject syntax elements into a code, wherein the syntax elements specify independent functions to be coalesced into a single loop, and data accesses to be coalesced for each function;
execute the pipeline, wherein the pipeline comprises the coalesced functions and data accesses.
22. The at least one machine readable medium of claim 21, wherein the syntax elements are data attributes that describe the organization of the data.
23. The at least one machine readable medium of claim 21, wherein the syntax elements are compute attributes that describe the data types, functions, and buffer sizes to be coalesced.
24. The at least one machine readable medium of claim 21, wherein injecting syntax elements comprises automatically inferring the syntax elements using compiler flags.
25. The at least one machine readable medium of claim 21, wherein injecting syntax elements comprises automatically inferring the syntax elements using static code analysis.
26. The at least one machine readable medium of claim 21, wherein injecting syntax elements comprises explicitly indicating the syntax elements using pragmas or special data types.
27. The apparatus of claim 21, where a run time system generates optimized machine code using syntax elements which executes on a target processor.