What is claimed is:
1. A method of processing first header information of a reception packet to provide instruction regarding processing of second header information, the method comprising the steps of:
(a) separating error correction data, payload data and first header information from the reception packet; and
(b) processing, in one clock cycle, the first header information in a protocol processor unit to provide, by an end of the one clock cycle, selected instructions for processing second header information.
2. The method of claim 1, further comprising:
generating payload flags based on the selected instructions, wherein
the payload flags are used by execution units for processing the accompanying payload data.
3. The method of claim 1, wherein the selected instructions are stored in at least one look up table and provided based on results of processing the first header information.
4. The method of claim 1, wherein the second header information is header information immediately following the first header information.
5. The method of claim 1, wherein step (b) comprises:
separating at least one field in the first header information for processing,
wherein the processing includes one of:
comparing the at least one field to predetermined data, and
processing the at least one field in an arithmetic and logic unit;
generating control signals and flags based on results of the comparing and processing;
matching the control signals and flags to instructions provided in a first lookup table; and
providing the selected instructions for processing the second header information based on the matched control signals and flags.
6. The method of claim 5, wherein a plurality fields are separated from the first header information, including at least a first field and a second field, where
the first field is compared to the predetermined data, and
the second field is processed in the arithmetic and logic unit.
7. The method of claim 1, wherein step (b) comprises:
separating a plurality of fields in the first header information;
comparing the plurality of fields with a plurality of parameters supplied from a second look-up table, simultaneously, using a plurality of comparators in a compare unit;
generating a match flag indicating a match between at least one of the plurality of fields and one of the plurality of parameters;
generating an address based on a result of the comparing;
matching the address to a value in a third look up table; and
using the matched value and the match flag to provide instructions for processing the second header information.
8. The method of claim 7, where the third look up table includes a plurality of individual look up tables, wherein
a first control signal provided from an instruction decoder selects one of the plurality of individual lookup tables in the third look up table, and
the address is matched to the value in the selected individual lookup table.
9. The method of claim 5, wherein when the step of comparing the at least one field to the predetermined value further comprises:
comparing a portion of the at least one field to the predetermined value when he at least one field is longer than a length of a comparator to generate a partial comparison result;
outputting the partial comparison result as long as a previous partial comparison result is a predetermined value; and
repeating the comparing step for each portion of the at least one field.
10. The method of claim 1, wherein margins between protocol layers of the header information are eliminated prior to processing.
11. The method of claim 1, wherein the error detection data is processed in parallel simultaneously with the processing of the header information.
12. A protocol processor for processing first header information of a reception packet to provide instructions for processing second header information, comprising:
a buffer adapted to buffer header information separated out from the reception packet; and
a protocol processor unit adapted to process, in one clock cycle, the first header information sent from the buffer to provide, by an end of the first clock cycle, instructions regarding processing of the second header information of the reception packet.
13. The protocol processor of claim 12, wherein the protocol processor comprises a payload flag generating unit to generate payload flags based on the instructions, wherein
the payload flags are used by execution units to guide processing of the accompanying payload data.
14. The protocol processor of claim 12, further comprising at least one look up table in which the selected instructions are stored, wherein the selected instructions are provided based on results of precessing of the first header information.
15. The protocol processor of claim 12, wherein the second header information is header information immediately following the first header information.
16. The protocol processor according to claim 12, wherein the protocol processor unit further comprises:
a multiple field extractor adapted to extract at least one field of the first header information, where the at least one field is passed to one of:
a compare unit adapted to compare the at least one field to a predetermined value, and
an arithmetic and logic unit adapted to process the at least one field to provide updated connection state variables which are stored in a register file and arithmetic and logic unit flags;
a program control flag generation unit adapted to generate control signals and flags based on a result from the compare unit and the flags and state variables provided by the arithmetic logic unit; and
a program and instruction decoding unit adapted to match (a) the control signals and flags generated by the program control flag generating unit and (b) instructions in a first look up table, and to output selected instructions that match the control signals and flags, wherein the selected instructions are used in processing the second header information.
17. The protocol processor of claim 16, wherein the multiple field extractor extracts a plurality of fields from the first header information including at least a first field and a second field, where
the compare unit compares the first field to the predetermined data, and
the arithmetic and logic unit processes the second field to provide updated connection state variables which are stored in the register file and arithmetic and logic unit flags.
18. The protocol processor of claim 12, wherein the buffer is capable of buffering data words of different sizes and comprises:
a plurality of registers, one of the plurality of registers storing the first header information separated out from the reception packet being processed, and other ones of the plurality of registers being used to buffer header information when necessary.
19. The protocol processor of claim 16, wherein the program and instruction decoding unit further comprises:
a next program counter calculation unit adapted to determined a next program counter value based on the control signals and flags provided by the program control flag generation unit;
a program counter adapted to receive the next program counter value provided by the next program counter calculation unit and determine a program counter value based on the next program counter value;
wherein the first lookup table matches (a) the program counter value provided by the program counter to (b) a selected instruction, and
an instruction decoder which receives the selected instruction from the first lookup table and decodes the instruction to provide decoded instructions used in decoding the second header information.
20. The protocol processor according to claim 12, further comprising:
a plurality of comparators adapted to perform a plurality of comparisons located in the compare unit;
a second look up table which receives a vector input and outputs a vector, parameters of which the at least one field is compared to using the plurality of comparators;
a flag to address translation unit which receives the result of the comparisons and generates a match flag indicating at least one of the plurality of parameters matches the at least one field of the first header information and an address corresponding to another flag generated based on a result of the multiple comparisons; and
a third look up table which receives the address from the flag to address translation unit which is matched to a value in a third look up table; wherein
the value matched in the third look up table and the match flag are passed to a next program counter calculation unit to provide a next program counter value which is passed to the program counter to be matched with an instruction in the first look up table to provide instructions for processing the second header information.
21. The protocol processor of claim 20, wherein the third look up table comprises a plurality of individual look up tables and a first control signal selects one of the plurality of look up tables and the address is matched to the value in the selected look up table.
22. The protocol processor unit of claim 16, wherein the compare unit compares a portion of the at least one field to the predetermined value when the at least one field is longer than a comparator to produce a partial comparison result, outputs the partial comparison result when a previous partial comparison result is of a predetermined value, and repeats the comparing for each portion of the at least one field.
23. The protocol processor of claim 12, further comprising:
an error correction accelerator unit adapted to process error correction data in parallel with the processing of first header information in the protocol processor unit.
24. The protocol processor of claim 12, wherein margins between protocol layers in the first header information are eliminated prior to processing in the protocol processor unit.
25. A program storage medium readable by a processor, tangibly embodying a program of instructions executed by the processor to perform method steps for processing first header information of a reception packet to provide instruction regarding processing of second header information, wherein the method steps comprise:
(a) separating error correction data, payload data and header information from the reception packet; and
(b) processing, in one clock cycle, the first header information in a protocol processor unit to provide, by an end of the one clock cycle, selected instructions for decoding second header information.
26. The program storage medium of claim 25, wherein the method steps further include:
generating payload flags based on the selected instructions, wherein
the payload flags are used by execution units to process the accompanying payload data.
27. The program storage medium of claim 23, wherein the selected instructions are stored in at least one look up table and are provided based on results of the processing of the first header information.
28. The program storage medium of claim 23, wherein the second header information is header information immediately following the first header information.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A connector connection structure, comprising:
a case having first and second surfaces extending in directions crossing each other at a first angle and an opening formed at said first surface;
a connector terminal portion inserted into said case from said opening;
a terminal block arranged in said case and connected to said connector terminal portion;
a closing portion having a first portion extending along said first surface and closing said opening, a second portion extending along said second surface, and a bent portion positioned between said first portion and said second portion and bent at a second angle being smaller than said first angle, and
a fastening member inserted into said case from above said second surface and fastening said case and said second portion of said closing portion.
2. The connector connection structure according to claim 1, wherein
said second angle is an acute angle.
3. The connector connection structure according to claim 1, wherein
said connector terminal portion and said terminal block are fixed to each other by an additional fastening member, and
said additional fastening member is inserted into said connector terminal portion and said terminal block from an identical direction as said fastening member.
4. The connector connection structure according to claim 1, wherein
a control apparatus controlling a rotating electric machine for driving a vehicle is arranged in said case.
5. A vehicle comprising the connector connection structure according to claim 1.
6. A connector connection method, comprising the steps of
storing a terminal block in a case having first and second surfaces extending in directions crossing each other at a first angle and an opening formed at said first surface;
inserting a connector terminal portion into said case from said opening, and arranging, on said case, a closing portion having a first portion positioned on said first surface, a second portion positioned on said second surface, and a bent portion positioned between said first portion and said second portion and bent at a second angle being smaller than said first angle; and
fastening said case and said second portion of said closing portion by a fastening member inserted from above said second surface while deforming said first portion of said closing portion so as to conform to said first surface positioned around said opening, thereby closing said opening by said first portion.