1. An on-die termination (ODT) circuit, comprising:
a first termination circuit including a first switch and configured to switchably connect a first termination impedance between an inputoutput data node and a first power supply voltage;
a second termination circuit including a second switch and configured to switchably connect a second termination impedance between the inputoutput data node and the first power supply voltage; and
a switch-control circuit configured to perform a logic operation on an output enable signal (DOEN) and an asynchronous control signal (ACS) to output a first switch-control signal and a second switch-control signal to selectively activate the first termination circuit and the second termination circuit, respectively, to selectively connect the first termination impedance, the second termination impedance, or both the first termination impedance and the second termination impedance between the inputoutput data node and the first power supply voltage;
wherein the first switch-control signal is not configured to control a switch to switchably connect a termination impedance between the inputoutput data node and a second power supply voltage during a memory READ mode nor during a memory WRITE mode;
wherein the second switch-control signal is not configured to control a switch to switchably connect a termination impedance between the inputoutput data node and the second power supply voltage during the memory READ mode nor during the memory WRITE mode.
2. An on-die termination (ODT) circuit, comprising:
a first termination circuit including a second switch and configured to switchably connect a first termination impedance between an inputoutput data node and a first power supply voltage;
a second termination circuit including a second switch and configured to switchably connect a second termination impedance between the inputoutput data node and the first power supply voltage; and
a switch-control circuit configured to perform a logic operation on an output enable signal (DOEN) and an asynchronous control signal (ACS) to output a first switch-control signal and a second switch-control signal to selectively activate the first termination circuit and the second termination circuit, respectively, to selectively connect the first termination impedance, the second termination impedance, or both the first termination impedance and the second termination impedance between the inputoutput data node and the first power supply voltage,
wherein the inputoutput data node receives data read out or written into a memory device, wherein
a first total impedance value is connected between the inputoutput data node and the first power supply voltage during a memory READ mode and based on a first set of predetermined logic levels of DOEN and ACS;
a second total impedance value, different from the first total impedance value, is connected between the inputoutput data node and the first power supply voltage during a memory WRITE mode and based on a second set of predetermined logic levels of DOEN and ACS;
a third total impedance value, different from the first and second total impedance values is connected between the inputoutput data node and the first power supply voltage during a memory normal mode and based on a third set of predetermined logic levels of DOEN and ACS.
3. The ODT circuit of claim 2, wherein: neither of the first termination circuit and the second termination circuit is activated during the memory READ mode;
and the first termination circuit is activated during the memory WRITE mode; and wherein both the first termination circuit and the second termination circuit are activated during the normal mode.
4. The ODT circuit of claim 2, wherein the second total impedance value is about 120 ohms for the memory WRITE mode, the third total impedance value is about 60 ohms during the NORMAL mode, and the first total impedance value is about zero during the memory READ mode.
5. The ODT circuit of claim 2, wherein the ACS signal is received at an external pin of the memory device and the inputoutput data node is connected to another external pin of the memory device.
6. The ODT circuit of claim 2, wherein the ACS signal is asynchronous with respect to a clock signal of the memory device.
7. The ODT circuit of claim 2, wherein the ACS signal is generated based on a memory WRITE command.
8. The ODT circuit of claim 7, further including a pulse generator configured to generate the ACS signal with a pulse width larger than the write data window.
9. The ODT circuit of claim 7, further including a command decoder configured to receive memory READ and WRITE commands from an external memory controller.
10. The ODT circuit of claim 2, wherein the DOEN signal is used to enable an output buffer of the memory device.
11. The ODT circuit of claim 2, wherein the first termination circuit comprises the first switch that responds to the first switch-control signal and at least one resistor.
12. The ODT circuit of claim 2, wherein the switch-control circuit comprises one of logic gates or at least one multiplexer.
13. The ODT circuit of claim 2, further comprising:
a third termination circuit configured to switchably connect a third termination impedance between the inputoutput data node the first power supply voltage; and
a third switch-control signal generated by the switch-control circuit to selectively activate the third termination circuit.
14. The ODT circuit of claim 13, wherein the second total impedance value is about 120 ohms, and wherein the third total impedance value is about 60 ohms, and wherein the first total impedance value is about 40 ohms.
15. A method of providing termination impedance at an inputoutput data line of a memory device, comprising:
performing a logic operation on an output enable (DOEN) signal and an asynchronous control signal (ACS) to output a first switch-control signal configured to selectively activate a first termination circuit having a first termination impedance and to output a second switch-control signal configured to selectively activate a second termination circuit having a second termination impedance,
wherein the first termination circuit is configured to switchably connect the first termination impedance between the inputoutput data line and a first power supply voltage,
wherein the second termination circuit is configured to switchably connect the second termination impedance between the inputoutput data line and the first power supply voltage,
wherein the ACS is asynchronous with respect to a clock signal of the memory device and is generated based on the presence of a memory WRITE command,
wherein the first switch-control signal activates the first termination circuit only if the memory WRITE command is present, and
wherein the DOEN signal is generated based on the presence of a memory READ command.
16. The method of claim 15, wherein a first total impedance value and a second total impedance value corresponding to a memory READ mode and a memory WRITE mode respectively, are alternately connected between the inputoutput data line and the first power supply voltage based on predetermined logic levels of DOEN and ACS.
17. The method of claim 16, wherein the DOEN signal is generated using an internal clock signal generated from an external clock signal, and the internal clock signal is turned off during memory WRITE and NORMAL modes.
18. The method of claim 15, wherein a first total impedance value is about 120 ohms for a memory WRITE operation, and wherein both the first termination circuit and the second termination circuit are activated during a NORMAL operation so that third total impedance values is about 60 ohms for the NORMAL operation, and wherein no termination circuit is activated for a memory READ operation.
19. The method of claim 15, wherein the ACS is generated by a memory controller and received at an external pin of the memory device and the inputoutput data line is connected to another external pin of the memory device.
20. The method of claim 15, further comprising decoding at the memory device commands issued from an external memory controller and generating the ACS based on a decode of the memory WRITE command.
21. The method of claim 19, wherein generating the ACS includes generating a pulse width larger than the write data window.
22. The method of claim 15, further comprising generating a third switch-control signal configured to selectively activate a third termination circuit to switchably connect a third impedance between the inputoutput data line and the first power supply voltage based on predetermined logic levels of DOEN and ACS.
23. The method of claim 22, wherein a total impedance value of about 120 ohms is connected between the inputoutput data line and the first power supply voltage for a memory WRITE; and a total impedance value of about 60 ohms is connected between the inputoutput data line and the first power supply voltage for a NORMAL operation; and a total impedance value of about 40 ohms of driver impedance is connected between the inputoutput data line and the first power supply voltage for a memory READ.
24. The ODT circuit of claim 3, wherein a logic level H at the DOEN indicates the memory READ mode and wherein a logic level L at the DOEN and a logic level H at the ACS indicates the memory WRITE mode, and wherein the presence of a logic level L at the DOEN and a logic level L at the ACS indicates the NORMAL mode.
25. The ODT circuit of claim 1, wherein the on-die termination (ODT) circuit does not include a switch configured to switchably connect a termination impedance between the inputoutput data node and the second power supply voltage in response to the first switch-control signal.
26. The ODT circuit of claim 25, wherein the on-die termination (ODT) circuit does not include a switch configured to switchably connect a termination impedance between the inputoutput data node and the second power supply voltage.
27. The ODT circuit of claim 25, further comprising: a third termination circuit including a third switch and configured to switchably connect a third termination impedance between the inputoutput data node and the first power supply voltage.
28. The ODT circuit of claim 27, further comprising: a fourth termination circuit including a fourth switch and configured to switchably connect a fourth termination impedance between the inputoutput data node and the second power supply voltage while neither of the first second termination impedance nor the second termination impedance is connected between the inputoutput data node and the first power supply voltage.
29. The method of claim 15, wherein the second switch-control signal activates the second termination circuit only if the memory READ command is NOT present.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A controller device for performing communication control of a mobile terminal belonging to an ad hoc network, comprising:
a communication environment information obtaining unit configured to obtain communication environment information, which shows a communication environment in the mobile terminal belonging to the ad hoc network, from the mobile terminal; and
a proxy control information transmitter unit configured to transmit proxy control information for performing the communication control instead of the controller device, to a predetermined mobile terminal belonging to the ad hoc network, when the obtained communication environment information satisfies a predetermined condition.
2. The controller device according to claim 1, comprising a communication control result receiver unit configured to receive a result of the communication control performed by the predetermined mobile terminal instead of the controller device, when a connection between the mobile terminal belonging to the ad hoc network and the controller device is recovered.
3. The controller device according to claim 1, wherein the communication environment information in the mobile terminal is a state of a radio wave in the mobile terminal.
4. The controller device according to claim 1, wherein the communication control of the mobile terminal is routing control performed through the ad hoc network.
5. A mobile terminal belonging to an ad hoc network, comprising:
a communication environment information transmitter unit configured to transmit to a predetermined controller device communication environment information which shows a communication environment in the mobile terminal;
a proxy control information receiver unit configured to receive proxy control information transmitted by the predetermined controller device, when the communication environment information satisfies predetermined conditions; and
a proxy controller unit configured to perform communication control of a mobile terminal belonging to the ad hoc network instead of the predetermined controller device based on the received proxy control information, when a connection between the mobile terminal and the predetermined controller device is cut at the latest.
6. The mobile terminal according to claim 5, comprising a communication control result transmitter unit configured to transmit to the predetermined controller device a result of the communication control performed instead of the predetermined controller device, when the connection between the mobile terminal and the controller device is recovered.
7. A mobile communication method for performing communication control of a mobile terminal belonging to an ad hoc network, comprising:
obtaining, at a controller device, communication environment information which shows a communication environment in the mobile terminal belonging to the ad hoc network from the mobile terminal;
transmitting, at the controller device, proxy control information for performing the communication control instead of the controller device to a predetermined mobile terminal belonging to the ad hoc network, when the obtained communication environment information satisfies predetermined conditions; and
performing, at the predetermined mobile terminal, the communication control of the mobile terminal belonging to the ad hoc network instead of the predetermined controller device based on the received proxy control information, when a connection between the mobile terminal belonging to the ad hoc network and the predetermined controller device is cut at the latest.