1. An insulated gate bipolar transistor (IGBT) comprising:
a gallium nitride (GaN) substrate with an upper surface;
a first GaN layer with a first conductive type, which is formed on the upper surface, wherein the first GaN layer has a side wall vertical to the upper surface;
a second GaN layer with a first conductive type, which is formed on the upper surface;
a third GaN layer with a second conductive type or an intrinsic conductive type, which is formed on the first GaN layer, wherein the third GaN layer and the GaN substrate are separated by the first GaN layer; and
a gate, which is formed on the GaN substrate, and has a side plate, which is directly or indirectly connected to the side wall in a lateral direction, for controlling a channel;
wherein the second GaN layer is separated from the first GaN layer by the gate.
2. The IGBT of claim 1, further comprising an aluminum gallium nitride (AlGaN) barrier layer, which is formed on the upper surface, and overlays the side wall, wherein the gate is separated from the GaN substrate and the first GaN layer by the AlGaN barrier layer.
3. The IGBT of claim 1, wherein the GaN substrate, the first GaN layer, the third GaN layer, and the gate form a junction field effect transistor (JFET), and the first GaN layer, the second GaN layer, and the GaN substrate form a bipolar junction transistor (BJT), wherein the JFET and the BJT are connected in parallel.
4. The IGBT of claim 2, wherein the GaN substrate, the first GaN layer, the third GaN layer, the AlGaN barrier layer, and the gate form a metal oxide semiconductor field effect transistor (MOSFET), and the first GaN layer, the second GaN layer, and the GaN substrate form a bipolar junction transistor (BJT), wherein the MOSFET and the BJT are connected in parallel.
5. A manufacturing method of an insulated gate bipolar transistor (IGBT) comprising:
providing a gallium nitride (GaN) substrate with an upper surface;
forming a first GaN layer with a first conductive type on the upper surface, wherein the first GaN layer has a side wall vertical to the upper surface;
forming a second GaN layer with a first conductive type on the upper surface;
forming a third GaN layer with a second conductive type or an intrinsic conductive type on the first GaN layer, wherein the third GaN layer and the GaN substrate are separated by the first GaN layer; and
forming a gate on the GaN substrate, which has a side plate, which is directly or indirectly connected to the side wall in a lateral direction, for controlling a channel;
wherein the second GaN layer is separated from the first GaN layer by the gate.
6. The manufacturing method of claim 5 further comprising: forming an aluminum gallium nitride (AlGaN) barrier layer on the upper surface, which overlays the side wall, wherein the gate is separated from the GaN substrate and the first GaN layer by the AlGaN barrier layer.
7. The manufacturing method of claim 5, wherein the GaN substrate, the first GaN layer, the third GaN layer, and the gate form a junction field effect transistor (JFET), and the first GaN layer, the second GaN layer, and the GaN substrate form a bipolar junction transistor (BJT), wherein the JFET and the BJT are connected in parallel.
8. The manufacturing method of claim 6, wherein the GaN substrate, the first GaN layer, the third GaN layer, the AlGaN barrier layer, and the gate form a metal oxide semiconductor field effect transistor (MOSFET), and the first GaN layer, the second GaN layer, and the GaN substrate form a bipolar junction transistor (BJT), wherein the MOSFET and the BJT are connected in parallel.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A dry etching method for forming a trench on a silicon substrate by plasma processing silicon of the silicon substrate by way of introducing a process gas into an airtight processing chamber, the method comprising:
a first process of conducting a plasma processing by introducing a mixture gas at least including HBr and N2 as the process gas to thereby round a boundary between a mask and an upper portion of a sidewall of the trench;
a second process of conducting a plasma processing to form the trench in the silicon of the silicon substrate; and
a third process of conducting a plasma processing by introducing a mixture gas including at least HBr and Cl2 as the process gas to thereby round a bottom portion of the trench.
2. The method of claim 1, wherein the first process is conducted under a condition where a pressure within the processing chamber is at most not greater than 6.7 Pa (50 mTorr); a ratio of a flow rate of HBr to a flow rate of N2 among the process gas is equal to or greater than 3; and a bias high frequency power applied to an electrode provided in the processing chamber to generate plasma is 100 W or larger.
3. The method of claim 1, wherein the third process is conducted under a condition where a pressure within the processing chamber is at least 20 Pa (150 mTorr) or greater; a ratio of a flow rate of HBr to a flow rate of Cl2 among the process gas is equal to or greater than 2; and a bias high frequency power applied to an electrode provided in the processing chamber to generate plasma is 50 W or larger.
4. The method of claim 1, wherein a time period during which the plasma processing is conducted in the first process is shorter than a time period during which the plasma processing is conducted in the second process.
5. The method of claim 4, wherein a ratio of the time period during which the plasma processing is conducted in the second process to the time period during which the plasma processing is conducted in the first process is 1 to 0.15\u02dc0.5.
6. The method of claim 1, wherein a time period during which the plasma processing is conducted in the third process is shorter than a time period during which the plasma processing is conducted in the second process.
7. The method of claim 6, wherein if a ratio of the time period during which the plasma processing is conducted in the second process to the time period during which the plasma processing is conducted in the third process is 1 to 0.3\u02dc0.7.