What is claimed is:
1. An integrated circuit chip with redundant elements, comprising:
a substrate die;
a plurality of microprocessors disposed in said substrate die, each microprocessor having a data interface;
a plurality of cache memories disposed in said substrate die, each cache memory having at least one memory interface for accessing the cache memory; and
a signal bus disposed in said substrate die, said signal bus including a programmable selector circuit for selecting a subset of said plurality of microprocessors to be used for processing information and for selecting a subset of said plurality of cache memories, said selector circuit simultaneously linking the data interface of a first selected microprocessor to a memory interface of a first selected cache memory and linking the data interface of a second selected microprocessor to a memory interface of a second selected cache memory.
2. The integrated circuit chip of claim 1, wherein the substrate die comprises a conductive silicon substrate having at least one bulk region and at least one silicon-on-insulator region, the cache memories being dynamic random access memories residing on said at least one bulk region and the microprocessors residing on said at least one silicon-on-insulator region.
3. The integrated circuit chip of claim 1, wherein said signal bus is a broadband signal bus.
4. The integrated circuit chip of claim 1, wherein said signal bus further comprises at least one active element to regenerate a data signal coupled by the signal bus between the first selected microprocessor and the first selected cache memory.
5. The integrated circuit chip of claim 1, wherein the chip is a multiprocessor and there are a total of N microprocessors and a subset of N-1 microprocessors is selected for parallel processing by the selector circuit.
6. The integrated circuit chip of claim 5, wherein there are a total of N cache memories and said selector circuit selects subset of N-1 cache memories for parallel processing.
7. The integrated circuit chip of claim 5, wherein said cache memories are level-2 cache memory units.
8. The integrated circuit chip of claim 7, wherein one of said cache memories comprises a cache sized to provide the cache resources of a level-2 cache memory and a level-3 cache memory.
9. The integrated circuit chip of claim 1, wherein the chip is a multiprocessor and the signal bus couples the microprocessors as a parallel processor.
10. The integrated circuit chip of claim 9, wherein said plurality of microprocessors includes at least nine microprocessors.
11. The integrated circuit chip of claim 1 wherein said programmable selector circuit is a multiplexor circuit.
12. The integrated circuit chip of claim 1, wherein said cache memories include level-2 cache memories and level-3 cache memories and one microprocessor is coupled to one level-2 cache memory and to one level-3 cache memory by the signal bus.
13. A multiprocessor chip, comprising:
a silicon substrate die having at least one bulk region and at least one silicon-on-insulator region, the silicon-on-insulator region including a buried oxide layer residing a preselected distance between an outer surface layer of crystalline silicon;
a plurality of microprocessors, each said microprocessor formed in said at least one silicon-on-insulator region, each microprocessor having a data interface;
a plurality of dynamic random access memory (DRAM) cache memories formed in said at least one bulk region, each cache memory having a memory interface for accessing the cache memory; and
a high bandwidth signal bus formed on said substrate having interconnect wires for linking the data interface of one microprocessor to a corresponding memory interface of one of the cache memories as a parallel processor.
14. The multiprocessor of claim 13, wherein said signal bus includes a programmable selector circuit for selecting a subset of the components that are utilized by the parallel processor, whereby a defective component may be bypassed, the selected components being chosen from a group consisting of microprocessors, cache memories, and the interconnect wires of the signal bus.
15. The multiprocessor of claim 13, wherein said cache memories are comprised of trench DRAM memories.
16. The multiprocessor of claim 15, wherein said buried oxide layer has a thickness of less than 200 nanometers.
17. The multiprocessor of claim 16, further comprising a layer of ions disposed proximate the interface of the buried oxide layer and the surface layer of crystalline silicon, said ions having a polarity and dose selected to suppress backgate conduction.
18. The multiprocessor of claim 13, wherein said signal bus includes at least one active element to regenerate a signal coupled between a microprocessor and a cache memory.
19. The multiprocessor of claim 13, wherein one of the cache memories is a level-2 cache memory.
20. The multiprocessor of claim 13, wherein one of the cache memories has a data capacity sufficient to provide the function of a level-2 cache memory and a level-3 cache memory.
21. The multiprocessor of claim 13, wherein the cache memories comprise level-2 cache memories and level-3 cache memories.
22. A multiprocessor chip, comprising:
a silicon substrate die having at least one bulk region and at least one silicon-on-insulator region, the silicon-on-insulator region including a buried oxide layer residing a preselected distance below an outer surface layer of crystalline silicon;
a plurality of microprocessors, each said microprocessor formed in said at least one silicon-on-insulator region, each microprocessor having a data interface;
a plurality of dynamic random access memory (DRAM) level-2 cache memories formed in said at least one bulk region, each level-2 cache memory having a memory interface for accessing the memory; and
a high bandwidth signal bus formed on said substrate die having interconnect wires for linking the data interface of one microprocessor to a corresponding memory interface of one of the level-2 cache memories as a parallel processor, said signal bus including a programmable selector circuit for selecting a subset of said plurality of microprocessors and for selecting a subset of said cache memories to be used for parallel processing, said selector circuit simultaneously linking the data interface of a first selected microprocessor to the memory interface of a first selected cache memory and linking the data interface of a second selected microprocessor to the memory interface of a second selected cache memory, whereby a defective microprocessor or a defective cache memory may be bypassed.
23. The multiprocessor chip of claim 22, wherein the level-2 cache memories are sized to provide the function of off-chip level-2 cache memories and off-chip leve-3 cache memories.
24. The multiprocessor chip of claim 22, further comprising:
a second plurality of dynamic random access memory (DRAM) cache memories formed in said at least one bulk region, each cache memory of the second plurality of cache memories sized to provide the function of a level-3 cache memory and having a memory interface for accessing the memory, wherein said second plurality of cache memories is simultaneously coupled by said signal bus to the plurality of microprocessors with a first selected microprocessor linked to a first selected one of the second plurality of cache memories and with a second selected microprocessor linked to a second selected one of the second plurality of cache memories.
25. A method of forming a multiprocessor chip on a silicon substrate, comprising the steps of:
a) masking the substrate to form masked and unmasked regions;
b) implanting said substrate with an oxygen ion implant having an energy and dose selected to form an implanted region underneath the surface of the substrate in the unmasked regions and bulk regions in the masked regions;
c) annealing said substrate to form silicon-on-insulator in said implanted region;
d) forming dense microprocessors in said implanted region via deep ultraviolet lithography;
e) forming dynamic random access memory units in the bulk region of said substrate; and
f) forming a signal bus for coupling said memory units to said microprocessors via a signal bus.
26. The method of claim 25, further comprising the step of implanting a backgate conduction suppression charge layer proximate the interface of the silicon dioxide and the surface layer of crystalline silicon to suppress parasitic backgate conduction.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A memory cell comprising:
(a) a semiconductor substrate (1) provided with a first diffusion layer (8) and a second diffusion layer (8) on a substrate surface;
(b) a floating gate insulating film (9) on said substrate surface and a floating gate (11) on said floating gate insulating film (9);
(c) a selection gate insulating film (2) on said substrate surface and a selection gate (4) on said selection gate insulating film (2);
(d) a control gate insulating film (12) on said substrate surface and a control gate (13) on said control gate insulating film (12);
said floating gate (11), selection gate (4) and control gate (13) being electrically insulated from one another, the first and second diffusion layers (8) being arranged as a source and a drain of a field effect transistor structure, and said floating gate (11) and selection gate (4) being arranged as series field effect gates in said field effect transistor structure, and said control gate (13) being arranged as a further field effect gate in said field effect transistor structure, in series with both said floating gate (11) and said selection gate (4).
2. A memory cell according to claim 1, wherein said floating gate (11) is a side wall spacer on an insulating side wall of said selection gate (4).
3. A memory cell according to claim 1 or 2, wherein a first intermediate insulating film (5, 12) separates said selection gate (4) from said control gate (13), and a second intermediate insulating film (12) separates said floating gate (11) from said control gate (13), said first intermediate insulating film (5, 12) being substantially thicker than said second intermediate insulating film (12).
4. A memory comprising a plurality of memory cells, each memory cell being arranged in accordance with any of the claims 1, 2 or 3, wherein
the memory cells are arranged in a plurality of rows and a plurality of columns, said rows extending in a row direction and said columns extending in a column direction;
the first diffusion layer (8) extends in said column direction to form interconnected, combined sources and drains of adjacent columns of memory cells in said column direction;
the second diffusion layer (8) extends in said column direction to form interconnected, combined sources and drains of adjacent columns of memory cells in said column direction;
selection gates (4) of memory cells in a column of memory cells are interconnected by a selection gate line (SG1; SG2; SG3) extending in said column direction;
control gates (13) of memory cells in a row direction are interconnected by a control gate line (CG1; CG2) extending in said row direction.
5. Process for making a memory cell comprising the following steps:
(a) providing a semiconductor substrate (1) of a first conductivity type;
(b) forming a selection gate insulating layer (2) on said substrate (1);
(c) forming a first conducting layer on said selection gate insulating layer (2);
(d) forming an additional insulating layer on said first conducting layer;
(e) etching said additional insulating layer, said first conducting layer and said selection gate insulating layer to form a selection gate (4) separated from said substrate by a selection gate insulating film (2) and having an additional insulating film (5) on top of it;
(f) forming a floating gate insulating layer;
(g) forming side wall spacers (11) adjacent to said selection gate (4) and separated from said selection gate (4) by said floating gate insulating layer;
(h) providing first and second diffusion layers (8) of a second conductivity type in said substrate (1) using said side wall spacers (11) and said additional insulating film (5) as a diffusion mask;
(i) etching a portion of said side wall spacers at one side of said selection gate (4) to form a floating gate (11) from a remaining portion of said side wall spacer at an opposite side of said selection gate (4);
(j) forming a control gate insulating layer (12);
(k) forming a control gate (13) on said control gate insulating layer (12).
6. Method for making a memory provided with memory cells, the memory cells being arranged in a plurality of rows and a plurality of columns, said rows extending in a row direction and said columns extending in a column direction; said method comprising the following steps:
(a) providing a semiconductor substrate (1) of a first conductivity type;
(b) forming a selection gate insulating layer (2) on said substrate (1);
(c) forming a first conducting layer on said selection gate insulating layer (2);
(d) forming an additional insulating layer on said first conducting layer;
(e) etching said additional insulating layer, said first conducting layer and said selection gate insulating layer to form selection gates (4) separated from said substrate by selection gate insulating films (2) and having additional insulating films (5) on top of them;
(f) forming a floating gate insulating layer;
(g) forming side wall spacers (11) adjacent to said selection gates (4) and separated from said selection gates (4) by said floating gate insulating layer;
(h) providing diffusion layers (8) of a second conductivity type in said substrate (1) using said side wall spacers (11) and said additional insulating films (5) as a diffusion mask;
(i) etching portions of said side wall spacers at first sides of said selection gates (4) to form floating gates (11) from remaining portions of said side wall spacers at second sides opposite said first sides of said selection gates (4);
(j) forming a control gate insulating layer (12);
(k) forming a control gate layer (13) on said control gate insulating layer (12);
(l) forming control gates (13) in said control gate layer.
7. Method according to claim 6, wherein selection gates of adjacent memory cells in said column direction are interconnected to form a selection gate line, said diffusion layers (8) and said selection gate line extending in said column direction, and control gates (13) of adjacent memory cells in said row direction being interconnected by a control gate line extending in said row direction.
8. Method of either programming or deprogramming a memory cell, the memory cell comprising:
(a) a semiconductor substrate (1) provided with a first diffusion layer (8) and a second diffusion layer (8) on a substrate surface;
(b) a floating gate insulating film (9) on said substrate surface and a floating gate (11) on said floating gate insulating film (9);
(c) a selection gate insulating film (2) on said substrate surface and a selection gate (4) on said selection gate insulating film (2);
(d) a control gate insulating film (12) on said substrate surface and a control gate (13) on said control gate insulating film (12);
said floating gate (11), selection gate (4) and control gate (13) being electrically insulated from one another, the first and second diffusion layers (8) being arranged as a source and a drain of a field effect transistor structure, said floating gate (11) and selection gate (4) being arranged as series field effect gates in said field effect transistor structure, and said control gate (13) being arranged as a further field effect gate in said field effect transistor structure, in series with both said floating gate (11) and said selection gate (4), and said method comprising the following step:
applying predetermined voltages to said control gate (13), said selection gate (4) and said first and second diffusion layers, such that said floating gate is either charged or discharged by Folwer-Nordhein tunneling.
9. Method of reading a memory cell, the memory cell comprising:
(a) a semiconductor substrate (1) provided with a first diffusion layer (8) and a second diffusion layer (8) on a substrate surface;
(b) a floating gate insulating film (9) on said substrate surface and a floating gate (11) on said floating gate insulating film (9);
(c) a selection gate insulating film (2) on said substrate surface and a selection gate (4) on said selection gate insulating film (2);
(d) a control gate insulating film (12) on said substrate surface and a control gate (13) on said control gate insulating film (12);
said floating gate (11), selection gate (4) and control gate (13) being electrically insulated from one another, the first and second diffusion layers (8) being arranged as a source and a drain of a field effect transistor structure, said floating gate (11) and selection gate (4) being arranged as series field effect gates in said field effect transistor structure, and said control gate (13) being arranged as a further field effect gate in said field effect transistor structure, in series with both said floating gate (11) and said selection gate (4), and said method comprising the following step:
applying predetermined voltages to said control gate (13), said selection gate (4) and said first and second diffusion layers, such that conducting channels are formed in said substrate surface between said first and second diffusion layers and below both said control gate (13) and said selection gate (4).