1. A method for exposing an edge of a wafer in a photolithographic process, comprising the steps of:
(a) aligning a notch of the wafer disposed on a wafer chuck of an orientation flatness (OF) detecting system using a wafer notch-detecting sensor;
(b) performing a wafer edge exposure (WEE) process on the notch-aligned wafer;
(c) carrying the wafer to a wafer stage and then performing a wafer EGA alignment; and
(d) exposing the EGA aligned wafer.
2. The method of claim 1, further comprising disposing the wafer on the wafer chuck such that a center of the wafer is aligned with a center of the wafer chuck.
3. The method of claim 1, wherein step (a) comprises detecting the center of the wafer by a wafer center position detecting sensor unit, before disposing the wafer on the wafer chuck.
4. The method of claim 1, wherein step (c) is performed while exposing a preceding wafer.
5. An orientation flatness (OF) detecting system, comprising:
(a) a wafer loader arm able to carry a wafer;
(b) a wafer center position detecting sensor unit adapted to detect a center of the wafer;
(c) a rotatable wafer chuck on which the wafer is to be disposed;
(d) a wafer notch detecting sensor unit adapted to detect a notch of the wafer; and
(e) a wafer edge exposure (WEE) apparatus including a WEE unit adapted to expose an edge of the wafer disposed on the wafer chuck, and a WEE driving unit able to move the WEE unit.
6. The OF detecting system of claim 4, wherein the WEE driving unit is configured to move the WEE unit in a radial direction of the wafer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A resonant clock system comprising:
a driver component configured to generate a driven input signal, wherein the driver component includes a plurality of drivers having varied sizes;
a clock load capacitor configured to receive the driven input signal;
an inductor array configured to have an effective inductance according to a selected frequency and to generate a resonant clock output signal at the selected frequency; and
a configuration controller configured to provide inductor configuration information to the inductor array and provide driver configuration information to the driver component, wherein the driver configuration information is configured to continuously enable a first power level from a first driver while continuously disabling power from a second driver throughout provision of a first selected frequency.
2. The system of claim 1, wherein the selected frequency is one of a plurality of available frequencies.
3. The system of claim 2, wherein the effective inductance is one of a plurality of available effective inductances.
4. The system of claim 1, wherein the driver component includes a plurality of drivers of varied sizes and the driver component is configured to utilize one of the plurality of drivers according to the selected frequency.
5. The system of claim 1, wherein the driver component is configured to receive a phase locked loop (PLL) signal as an input signal.
6. The system of claim 1, wherein the effective inductance has an inductive reactance equal to a capacitive reactance of the clock capacitor at the selected frequency.
7. The system of claim 1, wherein the inductor configuration information corresponding to a new selected frequency.
8. The system of claim 1, wherein the inductor array includes a plurality of inductors.
9. The system of claim 8, wherein the inductor array further includes switches coupled to the inductors, the switched configured to operate according to inductor configuration information.
10. The system of claim 8, wherein the plurality of inductors are connected in series.
11. The system of claim 8, wherein the plurality of inductors are connected in parallel.
12. The system of claim 1, wherein the driver configuration information is further configured to continuously enable a second power level from the second driver while continuously disabling the first driver throughout provision of a second selected frequency.
13. The system of claim 12, wherein the first driver has a first size that is greater than a second size of the second driver, the first power level is greater than the second power level, and the first frequency is greater than the second frequency.
14. A resonant clock system comprising:
a driver component configured to generate a driven input signal;
a clock load capacitor configured to receive the driven input signal;
an inductor array configured to have an effective inductance according to a selected frequency and to generate a resonant signal at the selected frequency; and
an inductor configuration component configured to automatically generate and provide inductor configuration information to the inductor array, the inductor configuration information generated according to the resonant signal and a PLL signal.
15. The system of claim 14, wherein the inductor configuration component includes a frequency comparator configured to receive the PLL signal and the resonant signal and a state machine configured to generate the inductor configuration information according to an output signal of the frequency comparator.
16. A resonant clock system comprising:
a PLL configured to generate a PLL signal;
a driver component configured to receive the PLL signal and to provide a driven signal;
an inductor array configured to receive the driven signal and to provide a resonant signal; and
an inductor configuration component configured to provide inductor configuration information to the inductor array according to the PLL signal;
wherein the inductor configuration component includes a frequency detector to detect frequencies of the PLL signal and the resonant signal.
17. A resonant clock system comprising:
a PLL configured to generate a PLL signal;
a driver component configured to receive the PLL signal and to provide a driven signal;
an inductor array configured to receive the driven signal and to provide a resonant signal; and
an inductor configuration component configured to provide inductor configuration information to the inductor array according to the PLL signal;
wherein the inductor configuration component includes a PLL counter and a resonant signal counter, wherein the PLL counter counts cycles of the PLL signal and the resonant signal counter counts cycles of the resonant signal in a selected time interval.