1. A device comprising:
a memory with a first memory pad to an ith memory pad and a jth memory pad to a kth (1<i<j<k) memory pad;
an integrated circuit device, wherein the memory is stacked on the integrated circuit device, the integrated circuit device comprising:
a first pad to an ith pad connected to the first memory pad to the ith memory pad;
a jth pad to a kth pad connected to the jth memory pad to the kth (1<i<j<k) memory pad; and
at least one pad arranged between the ith pad and the jth pad, wherein the at least one pad is not connected to a memory pad of the memory and serves as a pad for inputting or outputting a signal between an external device and the integrated circuit device, and
a power supply pad that is not connected to a substrate that supports the first pad to the ith pad, the jth pad to the kth pad and the at least one pad but is instead arranged on the memory between the ith memory pad and the jth memory pad, wherein the power supply pad is not connected to the first pad to the ith pad, the jth pad to the kth pad and the at least one pad.
2. The device according to claim 1, further comprising a control unit that performs read-control and write-control over data in the memory, wherein
the control unit performs read-control and write-control over data of the memory in a stack mode in which a chip of the memory is stacked on the integrated circuit device and performs read-control and write-control over data of an external memory in a non-stack mode in which the chip of the memory is not stacked on the integrated circuit device; and
the at least one pad arranged between the ith pad and the jth pad serves as a non-stack mode pad for outputting or inputting at least one of a data signal, an address signal and a control signal from or to the external memory in the non-stack mode.
3. The device according to claim 1, wherein no memory pad is arranged between the ith memory pad and the jth memory pad.
4. The device according to claim 3, wherein the relation: LDS\u22672LP, where LDS is a distance between the ith memory pad and the jth memory pad and LP is the arrangement pitch between memory pads, is satisfied.
5. The device according to claim 1, wherein the first memory pad to the ith memory pad and the jth memory pad to the kth memory pad are included in a first memory pad group arranged along a first chip side of the chip of the memory or included in a second memory pad group arranged along a third chip side on the opposite of the first chip side of the chip of the memory; and
the first pad to the ith pad and the jth pad to the kth pad are included in a first pad group arranged along a first side of the integrated circuit device or included in a second pad group arranged along a third side on the opposite side of the first side of the integrated circuit device.
6. The device according to claim 5, wherein
the memory is an image memory that stores image data; and
a control unit performs display control over an electro-optical apparatus on the basis of image data stored in the image memory.
7. The device according to claim 6, comprising:
the first pad group arranged along the first side of the integrated circuit device and connected to the first memory pad group arranged along the first chip side of the chip of the image memory;
the second pad group arranged along the third side of integrated circuit device and connected to the second memory pad group arranged along the third chip side of the chip of the image memory; and
a third pad group that receives the output of a data signal and a control signal for display control over the electro-optical apparatus and are arranged along a second side crossing the first side and the third side of the integrated circuit device.
8. The device according to claim 7, further comprising a fourth pad group for host interface, wherein
the fourth pad group is arranged along a fourth side on the opposite side of the second side of the integrated circuit device.
9. The device according to claim 7, further comprising a fifth pad group that receives the output of a signal for control over a power supply circuit in the electro-optical apparatus, wherein
the fifth pad group is arranged along the second side of the integrated circuit device.
10. The device according to claim 7, wherein
the control unit performs display control over the electro-optical apparatus on the basis of the image data from the image memory in the stack mode in which the chip of the image memory is stacked on the integrated circuit device and performs display control over the electro-optical apparatus on the basis of external image data from an external image memory in the non-stack mode in which the chip of the image memory is not stacked on the integrated circuit device.
11. The device according to claim 10, further comprising a stack identification pad that is set to a first power supply voltage in the stack mode with a bonding wire and is set to a second power supply voltage in the non-stack mode with the bonding wire.
12. The device according to claim 7, further comprising:
a host interface that performs interface processing tofrom a host; and
an information register that provides information to the host,
wherein
the information register stores instruction select information for selecting instruction code information describing instruction code, the instruction code configuring a command issued by the host;
the instruction code information selected on the basis of the instruction select information stored in the information register from a plurality of instruction code information pieces is loaded to an information memory when electronic equipment including the electro-optical apparatus is utilized; and
the control unit performs operational control over the integrated circuit device on the basis of the command issued by the host and the instruction code information read from the information memory when the electronic equipment operates.
13. The device according to claim 12, wherein
the information register stores stack identification information for identifying, as the instruction select information, the stack mode in which the chip of the image memory that stores image data is stacked on the integrated circuit device or the non-stack mode in which the chip of the image memory is not stacked on the integrated circuit device.
14. The device according to claim 13, wherein
in the stack mode, when the electronic equipment is utilized, instruction code information for the stack mode from the plurality of instruction code information pieces is loaded to the information memory, and, when the electronic equipment operates, operational control is performed over the integrated circuit device on the basis of the command issued by the host and the instruction code information for the stack mode; and
in the non-stack mode, when the electronic equipment is utilized, instruction code information for the non-stack mode from the plurality of instruction code information pieces is loaded to the information memory, and, when the electronic equipment operates, operational control is performed over the integrated circuit device on the basis of the command issued by the host and the instruction code information for the non-stack mode.
15. The device according to claim 13, further comprising a stack identification pad that is set to a first power supply voltage with a bonding wire in the stack mode and is set to a second power supply voltage with a bonding wire in the non-stack mode, wherein
the information register stores the stack identification information set on the basis of the voltage of the pad for stack identification.
16. Electronic equipment comprising the device according to claim 1.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A light quantity measuring device comprising:
a first light reception element that receives a predetermined incident light at a first light reception surface;
a second light reception element that receives the incident light at a second light reception surface, which is oriented in the same direction as the first light reception surface;
an identification circuit that identifies an incident angle of the incident light with respect to the first light reception surface; and
a selection circuit that, when the incident angle differs from a desired incident angle, selectively electrically connects an output portion of the second light reception element to an output portion of the first light reception element.
2. The light quantity measuring device according to claim 1, wherein a plurality of the second light reception elements are provided, and the respective light reception surfaces thereof have different areas.
3. The light quantity measuring device according to claim 2, wherein the selection circuit selectively electrically connects the output portions of the second light reception elements with the output portion of the first light reception element, so as to compensate for a reduction in a received light quantity due to the incident angle differing from the desired incident angle, via switching elements that, individually and in parallel, switch between connecting or not connecting at least one of the plurality of second light reception elements to the first light reception element.