1. An information processing system that includes a plurality of sets of two or more multiple processors that perform processing in synchronization with each other, comprising:
a non-volatile memory that stores a firmware program activating the multiple processors to a state in which the multiple processors are synchronized with each other;
a volatile memory that is defined by one address map as a whole;
a firmware copying section that copies the firmware program stored in the non-volatile memory to the volatile memory, on system boot;
a volatile memory address register in which an address of the volatile memory and of a copy destination to which the firmware program is copied is stored;
a volatile memory address storing section that stores the address of the volatile memory and of the copy destination to which the firmware program is copied by the firmware copying section, in the volatile memory address register;
a loss-of-synchronism detection section that detects loss of synchronism of the multiple processors; and
an address replacing section that refers to the volatile memory address register in response to the loss of synchronism being detected by the loss-of-synchronism detection section, to replace an address for reading the firmware program stored in the non-volatile memory, with the address of the volatile memory and of the copy destination of the firmware program.
2. The information processing system according to claim 1, further comprising:
a copy flag register in which a copy flag indicating that the firmware program is copied to the volatile memory is stored; and
a copy flag storing section that stores the copy flag in the copy flag register, in response to the firmware program being copied to the volatile memory by the firmware copying section, wherein
the address replacing section refers to the copy flag register in response to the loss of synchronism being detected by the loss-of-synchronism detection section, and when the copy flag is stored in the copy flag register, replaces the address for reading the firmware program stored in the non-volatile memory, with the address of the volatile memory and of the copy destination of the firmware program.
3. The information processing system according to claim 1, further comprising:
a context saving section that saves a context for continuing operation after resynchronization into the volatile memory, prior to reading of the firmware program, in response to the loss of synchronism being detected by the loss-of-synchronism detection section; and
a context reading section that reads the context saved into the volatile memory, after the firmware program is read out.
4. The information processing system according to claim 2, further comprising:
a context saving section that saves a context for continuing operation after resynchronization into the volatile memory, prior to reading of the firmware program, in response to the loss of synchronism being detected by the loss-of-synchronism detection section; and
a context reading section that reads the context saved into the volatile memory, after the firmware program is read out.
5. An information processing system that includes a plurality of sets of two or more multiple processors, and a system management device managing the plurality of sets of multiple processors, comprising:
a non-volatile memory that stores a firmware program activating the multiple processors to a state in which the multiple processors are synchronized with each other;
a volatile memory that is defined by one address map as a whole;
a loss-of-synchronism detection section that detects loss of synchronism of the multiple processors, and reports the loss of synchronism to the system management device; and
a separation processing section that logically separates the multiple processors from the information processing system, upon receipt of a separation instruction from the system management device, wherein
the system management device includes a separation instructing section that instructs, in response to the system management device receiving a report on loss of synchronism in any of the plurality of sets of multiple processors, a processor continuing normal operation of first multiple processors in which the loss of synchronism has occurred, to logically separate the first multiple processors from the information processing system.
6. The information processing system according to claim 5, wherein the system management device includes an addition instructing section that provides an instruction of logically adding the first multiple processors to the information processing system, in response to completion of resynchronization in the first multiple processors after being logically separated.
7. The information processing system according to claim 5, wherein
the plurality of sets of multiple processors include second multiple processors logically separated from the information processing system, and
the system management device includes an entry instructing section that provides an instruction of making a logical entry of the second multiple processors into the information processing system, in response to the system management device receiving a report on loss of synchronism in any of the plurality sets of multiple processors, and
the separation instructing section makes logical separation from the information processing system after transferring processing performed in the first multiple processors to the second multiple processors newly entered the information processing system, in response to a separation instruction from the system management device.
8. The information processing system according to claim 7, wherein the separation processing section separating the first multiple processors informs the second multiple processors of an ID of the first multiple processors as an ID of the second multiple processors newly entered the information processing system, in response to the separation instruction from the system management device.
9. The information processing system according to claim 8, further comprising:
a context saving section that saves a context for continuing processing performed in the first multiple processors with the second multiple processors into the volatile memory, in response to the separation instruction from the system management device, when being in a position of the first multiple processors; and
a context reading section that reads the context from the volatile memory, when being in a position of the second multiple processors and newly entering the information processing system.
10. A resynchronization method in an information processing system including a plurality of sets of two or more multiple processors that perform processing in synchronization with each other, the information processing system including
a non-volatile memory that stores a firmware program activating the multiple processors to a state in which the multiple processors are synchronized with each other,
a volatile memory that is defined by one address map as a whole, and
a volatile memory address register in which an address of the volatile memory and of a copy destination to which a firmware program is copied is stored, and
the resynchronization method comprising:
copying the firmware program stored in the non-volatile memory to the volatile memory, on system boot;
storing the address of the volatile memory and of the copy destination of the firmware program, in the volatile memory address register;
detecting loss of synchronism of the multiple processors; and
replacing an address for reading the firmware program stored in the non-volatile memory, with the address of the volatile memory and of the copy destination of the firmware program, by referring to the volatile memory address register in response to the loss of synchronism being detected.
11. A resynchronization method in an information processing system including a plurality of sets of two or more multiple processors, and a system management device managing the plurality of sets of multiple processors, the information processing system including
a non-volatile memory that stores a firmware program activating the multiple processors to a state in which the multiple processors are synchronized with each other, and
a volatile memory that is defined by one address map as a whole, and
the resynchronization method comprising:
detecting loss of synchronism of the multiple processors, and reporting the loss of synchronism to the system management device; and
instructing, in response to the system management device receiving a report on loss of synchronism in any of the plurality of sets of multiple processors, a processor continuing normal operation of first multiple processors in which the loss of synchronism has occurred, to logically separate the first multiple processors from the information processing system, the separation being performed in the system management device; and
logically separating the first multiple processors from the information processing system, in response to a separation instruction from the system management device, the separation being executed in the processor continuing the normal operation of the first multiple processors.
12. A non-transitory storage medium that stores a firmware program executed in an information processing system including a plurality of sets of two or more multiple processors that perform processing in synchronization with each other,
the information processing system including
a non-volatile memory that stores a firmware program activating the multiple processors to a state in which the multiple processors are synchronized with each other,
a volatile memory that is defined by one address map as a whole, and
a volatile memory address register in which an address of the volatile memory and of a copy destination to which a firmware program is copied is stored, and
the firmware program causing the information processing system to operate as the information processing system comprising:
a firmware copying section that copies the firmware program stored in the non-volatile memory to the volatile memory, on system boot;
a volatile memory address storing section that stores the address of the volatile memory and of the copy destination to which the firmware program is copied by the firmware copying section, in the volatile memory address register;
a loss-of-synchronism detection section that detects loss of synchronism of the multiple processors; and
an address replacing section that refers to the volatile memory address register in response to the loss of synchronism being detected by the loss-of-synchronism detection section, to replace an address for reading the firmware program stored in the non-volatile memory, with the address of the volatile memory and of the copy destination of the firmware program.
13. A non-transitory storage medium that stores a firmware program executed in an information processing system including a plurality of sets of two or more multiple processors, and a system management device managing the plurality of sets of multiple processors, the information processing system including
a non-volatile memory that stores a firmware program activating the multiple processors to a state in which the multiple processors are synchronized with each other, and
a volatile memory that is defined by one address map as a whole, and
the firmware program causing the information processing system to operate as the information processing system comprising:
a loss-of-synchronism detection section that detects loss of synchronism of the multiple processors, and reports the loss of synchronism to the system management device; and
a separation processing section that logically separates the multiple processors from the information processing system, upon receipt of a separation instruction from the system management device.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A side pumping type DPSS laser, comprising:
a first laser chip for generating a pumping light;
a second laser chip, although being parallel with the first laser chip, slightly slanted to a predetermined degree so as to avoid a contact with the pumping light;
a first and second focusing lens for focusing the pumping lights; and
a side pumping medium for forming the focused pumping lights in a beam mode so as to output as a lasing light.
2. The side pumping type DPSS laser of claim 1, wherein the side pumping medium comprises:
a laser material manufactured in a plate type;
a sapphire plate formed at both sides of the laser material and having an AR coating and HR coating alternatively provided on each side of the laser material;
a copper block provided at a top of the sapphire plate for fixing the sapphire plate and transmitting heat to outside;
HR coating formed on a rear surface of the side pumping medium for reflecting radiated lasing light; and
PR coating formed on a front surface of the side pumping medium for transmitting a part of the lasing light.
3. The side pumping type DPSS laser of claim 2, further comprises a stop coating formed between the PR coating and the laser material for filtering all the pumping light, and a middle portion thereof is removed for filtering all lights except a light in a pumping light lasing mode.
4. The side pumping type DPSS laser of claim 2, wherein a width of the laser material is in a beam waist size of the lased laser.
5. The side pumping type DPSS laser of claim 2, wherein a doping amount of the laser material is a value of the pumping light radiated to and absorbed by the laser material after being transmitted through the laser material.
6. The side pumping type DPSS laser of claim 1, wherein perpendicular component of the light radiated to the predetermined surface is focused and parallel component thereof is proceeded parallel.
7. The side pumping type DPSS laser, comprising:
a first pumping laser diode (LD) generating a plurality of pumping lights;
a second pumping laser diode (LD) provided to be slightly slanted such that the pumping lights are not in contact with each other although being parallel around the side pumping medium;
a first and second focusing lens array having a plurality of focusing lens for focusing a plurality of the pumping lights; and
a side pumping assembly forming the focused pumping lights in a beam mode so as to output as a lasing light.
8. The side pumping type DPSS laser of claim 8, further comprises a stop coating formed between the PR coating and the laser material for filtering all the pumping light, and a middle portion thereof is removed for filtering all lights except a light in a pumping light lasing mode.
9. The side pumping type DPSS laser of claim 8, wherein a doping amount of the laser material is a value of the pumping light radiated to and absorbed by the laser material after being transmitted through the laser material.
10. The side pumping type DPSS laser of claim 8, wherein a width of the laser material is in a beam waist size of the lased laser
11. The side pumping type DPSS laser of claim 8, wherein a doping amount of the laser material is a value of the pumping light radiated to and absorbed by the laser material after being transmitted through the laser material.
12. The side pumping type DPSS laser of claim 7, wherein the focusing lens array focus perpendicular component light radiated to a predetermined surface and proceeds parallel component light parallel.