1. A video decoding method comprising:
obtaining a quantization parameter of a slice;
generating a predicted quantization parameter of a current quantization group using the quantization parameter of the slice, wherein the current quantization group is a first quantization group in a current row included in the slice;
generating, according to an availability of a neighboring block of the second quantization group in the current row, a predicted quantization parameter of a second quantization group in the current row included in the slice using a determined quantization parameter regarding the neighboring block of the second quantization group;
generating a predicted quantization parameter of a next quantization group using the quantization parameter of the slice, wherein the next quantization group is a first quantization group in a next row included in the slice; and
performing an inverse quantization on the current quantization group, the second quantization group in the current row, and the next quantization group,
wherein each of the current row and the next row comprises a plurality of largest coding units.
2. The video decoding method of claim 1, wherein the current quantization group is a set of at least one of coding units sharing the predicted quantization parameter of the current quantization group.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A synchronous semiconductor memory device operating in synchronization with an external clock comprising:
a data output buffer circuit for performing an output operation of read data to the outside requiring a processing time corresponding to an operating condition; and
a control clock generating circuit for generating a control clock activating said output operation of said data output buffer circuit according to said external clock,
said control clock generating circuit including:
a delay circuit for delaying said external clock to generate said control clock,
a delay control section controlling a delay time in said delay circuit according to a phase difference between said external clock and a feedback clock, and
a replica delay time adjusting section, provided between said delay circuit and said delay control circuit, and for delaying said control clock by a replica delay time corresponding to said processing time to generate said feedback clock, and
said replica delay time adjusting section adjusting said replica delay time according to said operating condition.
2. The synchronous semiconductor memory device according to claim 1, wherein said operating condition sets the number of bits of data communicated in a one time data input and output operations.
3. The synchronous semiconductor memory device according to claim 1, wherein said replica delay time adjusting section comprises:
a fixed delay circuit for delaying said control clock by a fixed first delay time; and
a delay adjusting section for further delaying said control clock by a second delay time according to said operating condition.
4. The synchronous semiconductor memory device according to claim 3, wherein said operating condition sets the number of bits of data communicated in a one time data input and output operations and
said first delay time is set in correspondence to said processing time in a case where said number of bits is set to the minimum.
5. The synchronous semiconductor memory device according to claim 1, wherein said replica delay time adjusting section comprises:
a delay capacitor for delaying said control clock; and
a switch circuit electrically coupled between a node transmitting said control clock and said delay capacitor, and
said switch circuit is turned on or off according to said operating condition.
6. The synchronous semiconductor memory device according to claim 5, wherein said delay capacitor includes a capacitor formed by a field effect transistor.
7. The synchronous semiconductor memory device according to claim 5, wherein said delay capacitor comprises: a PN junction capacitor formed on a semiconductor substrate.
8. The synchronous semiconductor memory device according to claim 5, wherein said delay capacitor comprises:
a plurality of sub delay capacitors formed on a semiconductor substrate;
a plurality of first interconnects electrically coupled to said plurality of sub delay capacitors, respectively, and formed in the same interconnection layer on said semiconductor substrate;
a second interconnect formed in said same interconnection layer and coupled to said node through said switch circuit; and
a third interconnect selectively formed in at least one of a plurality of regions of said same interconnection layer, corresponding to between each of said plurality of first interconnects and said second interconnect.
9. The synchronous semiconductor memory device according to claim 5, wherein said delay capacitor comprises:
a plurality of sub delay capacitors formed on a semiconductor substrate;
a plurality of first interconnects electrically coupled to said respective plurality of sub delay capacitors;
a second interconnect coupled to said node through said switch circuit; and
a plurality of program elements electrically coupled between of said plurality of first interconnects and said second interconnect, respectively, and
selection of electrical coupling or non-coupling in said plurality of program elements between corresponding one of said plurality of first interconnects and said second interconnect is externally set in a non-volatile manner.
10. The synchronous semiconductor memory device according to claim 1, wherein said replica delay time adjusting section comprises:
a plurality of delay resistors connected in parallel between a first node to which said control clock is transmitted and a second node from which said feedback clock is generated; and
a plurality of first switch circuits provided corresponding to said plurality of delay resistors, respectively, and turned on or off according to said operating condition, and
each of said first switch circuits is electrically coupled between one of said first and second nodes and a corresponding one of said plurality of delay resistors.
11. The synchronous semiconductor memory device according to claim 10, wherein said replica delay time adjusting section further comprises: a second switch circuit coupled directly between said first node and said second node and turned on or off according to said operating condition.
12. The synchronous semiconductor memory device according to claim 10, wherein each of said plurality of delay resistors comprises:
a plurality of sub delay resistors formed on a semiconductor substrate;
a plurality of first interconnects electrically coupled to said plurality of sub delay resistors, respectively, and formed in the same interconnection layer on said semiconductor substrate;
a second interconnect formed in said same interconnection layer and coupled to said one of said first and second nodes through said first switch circuit; and
a third interconnect selectively formed in at least one of a plurality of regions of said same interconnection layer, corresponding to between each of said plurality of first interconnects and said second interconnect.
13. The synchronous semiconductor memory device according to claim 10, wherein each of said plurality of delay resistors comprises:
a plurality of sub delay resistors formed on a semiconductor substrate;
a plurality of first interconnects electrically coupled to said plurality of sub delay resistors, respectively;
a second interconnect formed in said same interconnection layer and coupled to said one of said first and second nodes through said first switch circuit; and
a plurality of program elements electrically coupled between each of said plurality of first interconnects and said second interconnect, and
selection of electrical coupling or non-coupling in said plurality of program elements between corresponding one of said plurality of first interconnects and said second interconnect is externally set in a non-volatile manner.