1. A semiconductor memory device comprising:
a buffer configured to input a first signal and outputs a first delay signal;
a command decoder configured to output a second signal;
a mask pulse signal generator configured to input the first delay signal and the second signal and generate a mask pulse signal; and
a signal reshaper configured to input the first delay signal, the second signal and the mask pulse signal and reshape the first delay signal or the second signal,
wherein the first signal includes a data strobe signal for fetching a data signal at a constant interval, and the second signal includes an internal write command signal for performing a write operation.
2. The semiconductor memory device of claim 1, wherein the mask pulse signal generator is further configured to input at least one of a first information signal which includes information related to a preamble length of the first signal and a second information signal which includes information related to an operation of generating a position of the mask pulse signal.
3. The semiconductor memory device of claim 2, wherein the first information signal is a preamble information signal and the second information signal is at least one of a cyclic redundancy check (CRC) information signal or a burst length information signal.
4. The semiconductor memory device of claim 1, wherein the mask pulse signal generator includes a counter that is configured to count the number of pulses of the first delay signal.
5. The semiconductor memory device of claim 4, wherein the mask pulse signal generator is configured to generate the mask pulse signal using information related to the number of pulses of the first delay signal, counted by the counter from a reference point.
6. The semiconductor memory device of claim 5, wherein the reference point is a point at which a first rising edge portion of the first delay signal and a pulse of the second signal meet.
7. The semiconductor memory device of claim 1, further comprising a write flag signal generator configured to generate a write flag signal using the reshaped first delay signal or the reshaped second signal.
8. The semiconductor memory device of claim 1, wherein the signal reshaper is configured to reshape the first delay signal in order to prevent the first delay signal from toggling or to disable the second signal.
9. A method of operating a semiconductor memory device, the method comprising:
receiving a first signal and outputting a first delay signal;
outputting a second signal from a command decoder;
generating a mask pulse signal using the first delay signal and the second signal; and
receiving the first delay signal, the second signal, and the mask pulse signal and reshaping the first delay signal or the second signal,
wherein the first signal includes a data strobe signal for fetching a data signal at a constant interval, and the second signal includes an internal write command signal for performing a write operation.
10. The method of claim 9, wherein the generating of the mask pulse signal comprises generating the mask pulse signal using information related to the number of pulses of the first delay signal, counted from a reference point.
11. The method of claim 10, wherein the reference point is a point at which a first rising edge portion of the first delay signal and a pulse of the second signal meet.
12. The method of claim 11, wherein the reshaping of the first delay signal comprises synthesizing the first delay signal and the mask pulse signal in order to prevent the first delay signal from toggling.
13. The method of claim 11, wherein the reshaping of the first delay signal comprises synthesizing the first delay signal and the mask pulse signal to disable the second signal.
14. A semiconductor memory device comprising:
a mask pulse signal generator configured to receive a first delay signal and a second signal and generate a mask pulse signal; and
a signal reshaper configured to receive the first delay signal, the second signal and the mask pulse signal and reshape the first delay signal and the second signal.
15. The semiconductor memory device of claim 14, further comprising a buffer configured to input a first signal and outputs the first delay signal to the mask pulse signal generator.
16. The semiconductor memory device of claim 15, wherein the buffer is configured to output the first delay signal to the signal reshaper.
17. The semiconductor memory device of claim 14, further comprising a command decoder configured to output the second signal to the mask pulse signal generator.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for controlling a permanent magnet motor, the method comprising the steps of:
adjusting a first current command in response to a voltage error to produce a first adjusted current, the voltage error derived from a second current command during a voltage saturation of the permanent magnet motor;
limiting each of the first adjusted current and the second current command below a maximum current;
converting the first adjusted current to a first potential;
converting the second current command to a second potential; and
supplying the first and second potentials to the permanent magnet motor.
2. A method according to claim 1, wherein said limiting step comprises:
limiting the first adjusted current below a first current limit; and
limiting the second current command below a second current limit, the second current limit derived from the first adjusted current and the maximum current.
3. A method according to claim 1, wherein said limiting step comprises:
limiting the first adjusted current to a first predetermined maximum current to produce a first limited current; and
limiting the second current command between
I
s_max
2
–
(
i
ds_m
r
*
)
2
\u2062
\u2062
and
\u2062
–
I
s_max
2
–
(
i
ds_m
r
*
)
2
,
wherein Is\u2014max is a maximum stator current and ir*ds\u2014m is the first limited current.
4. A method according to claim 1, wherein the permanent magnet motor has a voltage limitation, and wherein said step of adjusting the first current command comprises:
determining a correction factor \u03c9rLs(vr*qs\u2212vr*qs);
low pass filtering the correction factor to produce a filtered value;
applying a predetermined control gain to the filtered value to produce a current adjustment; and
subtracting the current adjustment from the first current command to produce the first adjusted current;
wherein \u03c9r is a rotor speed of the permanent magnet motor, Ls is a machine per phase inductance, vr*qs is a q-axis reference voltage command derived from the second current command, and vrqs is a q-axis reference voltage derived from an application of the voltage limitation to vr*qs.
5. A method according to claim 1, wherein the permanent magnet motor has a voltage limitation, and wherein said step of converting the first adjusted current comprises:
converting the first adjusted current to a first voltage command; and
limiting the first voltage command below the maximum potential to produce the first potential.
6. A method according to claim 1, wherein the permanent magnet motor has a voltage limitation, and wherein said step of converting the second current command comprises:
converting the second current command to a second voltage command; and
limiting the second voltage command below the maximum potential to produce the second potential.
7. A method according to claim 6, wherein said step of adjusting comprises determining the voltage error from a difference between the second voltage command and the second potential.
8. A method for controlling a permanent magnet motor, the method comprising the steps of:
adjusting a first current command in response to a first voltage error to produce a first adjusted current, the first voltage error derived from a second current command during a voltage saturation of the permanent magnet motor;
adjusting the second current command in response to a second voltage error to produce a second adjusted current, the second voltage error derived from the first current command during the voltage saturation of the permanent magnet motor;
limiting each of the first adjusted current and the second adjusted current below a maximum current;
converting the first adjusted current to a first potential;
converting the second adjusted current to a second potential; and
supplying the first and second potentials to the permanent magnet motor.
9. A method according to claim 8, wherein said limiting step comprises:
limiting the first adjusted current below a first current limit; and
limiting the second adjusted current below a second current limit, the second current limit derived from the first current limit and the maximum current.
10. A method according to claim 8, wherein said limiting step comprises:
limiting the first adjusted current below a first predetermined maximum current to produce a first limited current reference; and
limiting the second adjusted current between
I
s_max
2
–
(
i
ds_m
\u2032
+
)
2
\u2062
\u2062
and
\u2062
–
I
s_max
2
–
(
i
ds_m
r
+
)
2
,
wherein Is\u2014max is the maximum current and ir*ds\u2014m is the first limited current reference.
11. A method according to claim 8, wherein the permanent magnet motor has a voltage limitation, and wherein the method further comprises prior to said step of adjusting the first current command:
producing a first voltage command for the second current command; and
determining the first voltage error from the first voltage command and the maximum voltage.
12. A method according to claim 8, wherein the permanent magnet motor has a maximum voltage, and wherein said step of adjusting the first current command comprises:
determining a correction factor \u03c9rLs(vr*qs\u2212vr*qs);
low pass filtering the correction factor to produce a filtered value;
applying a predetermined control gain to the filtered value to produce a current adjustment; and
subtracting the current adjustment from the first current command to produce the first adjusted current;
wherein \u03c9r is a rotor speed of the permanent magnet motor, Ls is a machine per phase inductance, vr*qs is a q-axis reference voltage command derived from the second current command, and vrqs is a q-axis reference voltage derived from the maximum voltage and vr*qs.
13. A method according to claim 8, wherein the permanent magnet motor has a maximum voltage, and wherein said step of adjusting the second current command comprises:
producing a second voltage command from the first current command; and
determining the second voltage error from the second voltage command and the maximum voltage.
14. A method according to claim 8, wherein the permanent magnet motor has a maximum voltage, and wherein said step of adjusting the second current command comprises:
determining a correction factor \u03c9rLs(vr*ds\u2212vr*ds);
band pass filtering the correction factor to produce a filtered value;
applying a predetermined control gain to the filtered value to produce a current adjustment, and
subtracting the current adjustment from the second command current to produce the second adjusted current;
wherein \u03c9r is a rotor speed of the permanent magnet motor, Ls is a machine per phase inductance, vr*ds is a d-axis reference voltage command derived from the second command current, and vrds is a d-axis reference voltage derived from the maximum voltage and vr*ds.
15. A method according to claim 8, wherein the permanent magnet motor has a voltage limitation, and wherein the method further comprises:
converting the first adjusted current to a first voltage reference command;
converting the second adjusted current to a second voltage reference command; and
limiting each of the first and second voltage reference commands to the maximum voltage.
16. A control system for regulating an input voltage to a permanent magnet motor having a saturation current, the controller comprising:
a first current compensation module configured to:
subtract a first error from a first current command to produce a first adjusted current; and
limit said first adjusted current to a first maximum current to produce a first limited current;
a second current compensation module configured to limit a second current command to a second maximum current to produce a second limited current, said second maximum current derived from said first maximum current and said saturation current; and
a transformation module coupled to said first and second current compensation modules for converting said first limited current to a first input voltage and for converting said second limited current to a second input voltage, said first error produced while converting said second limited current to said second input voltage.
17. A control system according to claim 16, wherein said first current compensation module comprises:
a low pass filter receiving said first error and producing a filtered signal;
a gain module coupled to said low pass filter for applying a control gain to said filtered signal; and
a summer coupled to said amplifier for comparing said first current command with said.
18. A control system according to claim 16, wherein said second current compensation module comprises a summer for adding said second limited current with a second error, said second error produced while converting said first limited current to said first input voltage.
19. A control system according to claim 18, wherein said second current compensation module further comprises:
a band pass filter receiving said second error and producing a filtered signal; and
a gain module coupled to said band pass filter for applying a control gain to said filtered signal.
20. A control system according to claim 16, wherein said transformation module comprises a voltage limitation module configured to:
receive first and second voltage commands, said first voltage command derived from said first limited current, said second voltage command derived from said second limited current;
limit said first voltage command to produce said first input voltage, said second error being a difference between said first voltage command and said first input voltage; and
limit said second voltage command to produce said second input voltage, said first error being a difference between said second voltage command and said second input voltage.