1. An optical fiber coupling assembly, comprising:
a first optical fiber connector comprising:
a main body comprising a first light guide, a first light source, and a first photoelectric conversion element;
a plug comprising a first optical lens; and
a first optical fiber optically aligned with the first light guide and the first optical lens; and
a second optical fiber connector defining a first passage capable of receiving the plug, the second optical fiber connector comprising:
a second optical lens received in the first passage and capable of coupling with the first optical lens when the plug is inserted in the first passage;
a second light guide;
a second optical fiber optically aligned with the second light guide and the second optical lens;
a second light source; and
a second photoelectric conversion element; wherein
when the first light source emits a first light signal having a first wavelength, the first light signal is transmitted by the first light guide, the first optical fiber, the first optical lens, the second optical lens, the second optical fiber, and the second light guide in sequence and is finally directed to the second photoelectric conversion element;
when the second light source emits a second light signal having a second wavelength, the second light signal is transmitted by the second light guide, the second optical fiber, the second optical lens, the first optical lens, the first optical fiber, and the first light guide in sequence and is finally directed to the first photoelectric conversion element; and
the first wavelength is different from the second wavelength.
2. The optical fiber coupling assembly of claim 1, wherein the first light guide and the second light guide are spectroscopes.
3. The optical fiber coupling assembly of claim 2, wherein the first light guide and the second light guide are triangular prisms.
4. The optical fiber coupling assembly of claim 3, wherein the first light guide comprises a first surface adjacent to the first optical fiber, a second surface adjacent to the first light source and the first photoelectric element, and a third surface connecting the first surface to the second surface; and the second light guide comprises a forth surface adjacent to the second optical fiber, a fifth surface adjacent to the second light source and the second photoelectric element, and a sixth surface connecting the forth source to the fifth surface.
5. The optical fiber coupling assembly of claim 4, wherein the third surface and the sixth surface are reflective surfaces.
6. The optical fiber coupling assembly of claim 1, wherein the first light source and the second light source are laser diodes.
7. The optical fiber coupling assembly of claim 1, wherein the first photoelectric element and the second photoelectric element are photodiodes.
8. The optical fiber coupling assembly of claim 1, wherein the plug defines a second passage; the first optical lens is mounted in the second passage; one end of the first optical fiber extends in the second passage and is connected with the first optical lens, and the other end of the first optical fiber extends out of the second passage and is aligned with the first light guide.
9. The optical fiber coupling assembly of claim 8, wherein one end of the second optical fiber extends in the first passage and is connected with the second optical lens, and the other end of the second optical fiber is aligned with the second light guide.
10. The optical fiber coupling assembly of claim 9, wherein the end of the first optical fiber connected with the first optical lens is positioned at a focus surface of the first optical lens; the end of the second optical fiber connected with the second optical lens is positioned at a focus surface of the second optical lens.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A data transfer control device which includes a buffer controller which allocates a plurality of pipe regions in a packet buffer and controls access to the packet buffer, each of the pipe regions storing data transferred to or from corresponding one of endpoints, and a transfer controller which controls data transfer between each of the pipe regions and corresponding one of the endpoints, the data transfer control device comprising:
an address translation table which stores pipe region numbers each of which is assigned to at least one of divided blocks, the divided blocks being obtained by dividing a memory region of the packet buffer, and generates a physical access address of the packet buffer based on the stored pipe region numbers, a pipe region number to which access is requested, and a relative access address of the pipe regions; and
a region allocator which performs reconstruction processing of the pipe regions by changing the pipe region number assigned to the divided block of the packet buffer, the reconstruction processing including at least one of processing of deleting the allocated pipe region, processing of adding a new pipe region, and processing of changing a size of the pipe region.
2. The data transfer control device as defined in claim 1,
wherein the address translation table includes:
a plurality of block registers, each of the block registers storing the pipe region number assigned to the divided block;
comparators which compare the pipe region numbers stored in the block registers with the pipe region number to which access is requested; and
an address decoder which generates the physical access address based on comparison results of the comparators and the relative access address of the pipe regions.
3. The data transfer control device as defined in claim 1,
wherein the region allocator calculates a number of the divided blocks necessary for allocating each of the pipe regions based on a page size and a number of pages of each of the pipe regions, and assigns the pipe region number to each of the divided blocks based on the calculated number of the divided blocks.
4. The data transfer control device as defined in claim 1,
wherein the region allocator reads the pipe region numbers assigned to the divided blocks from the address translation table, and, on condition that clearance of the pipe region specified by the read pipe region number is permitted, performs rewrite processing of the read pipe region number.
5. The data transfer control device as defined in claim 1,
wherein the region allocator:
includes a block number counter which counts divided block numbers, and a plurality of number-of-blocks counters, a number of the divided blocks necessary for allocating each of the pipe regions being set in each of the number-of-blocks counters as a counter value;
reads the pipe region numbers assigned to the divided blocks from the address translation table based on the divided block numbers from the block number counter; and,
each time the pipe region number is assigned to the divided block, decrements a number of blocks set in the number-of-blocks counter corresponding to the assigned pipe region number.
6. The data transfer control device as defined in claim 1,
wherein the buffer controller controls access to the pipe region of the packet buffer based on a pointer which indicates the relative access address of the pipe region.
7. A data transfer control device which includes a buffer controller which allocates a plurality of pipe regions in a packet buffer and controls access to the packet buffer, each of the pipe regions storing data transferred to or from corresponding one of endpoints, and a transfer controller which controls data transfer between each of the pipe regions and corresponding one of the endpoints, the data transfer control device comprising:
an address translation table which translates a logical access address of the packet buffer into a physical access address of the packet buffer; and
a region allocator which performs reconstruction processing of the pipe regions by changing correspondence between the logical access address and the physical access address in the address translation table, the reconstruction processing including at least one of processing of deleting the allocated pipe region, processing of adding a new pipe region, and processing of changing a size of the pipe region;
wherein the region allocator changes the correspondence between the logical access address and the physical access address for a first pipe region allocated in the packet buffer before and after the reconstruction processing corresponding to a first endpoint so that the physical access address does not change even when the logical access address of the first pipe region changes.
8. The data transfer control device as defined in claim 1,
wherein the data transfer control device performs pause processing of pausing data transfer between the pipe regions and the endpoints,
wherein the data transfer control device performs the reconstruction processing of the pipe regions after the pause processing of the data transfer has been completed, and
wherein the data transfer control device resumes the data transfer which has been paused after the reconstruction processing of the pipe regions.
9. The data transfer control device as defined in claim 7,
wherein the data transfer control device performs pause processing of pausing data transfer between the pipe regions and the endpoints,
wherein the data transfer control device performs the reconstruction processing of the pipe regions after the pause processing of the data transfer has been completed, and
wherein the data transfer control device resumes the data transfer which has been paused after the reconstruction processing of the pipe regions.
10. The data transfer control device as defined in claim 8, comprising:
a register which stores instruction information for the pause processing of the data transfer; and
a register which stores information which indicates that the pause processing has been completed for all of the pipe regions.
11. The data transfer control device as defined in claim 9, comprising:
a register which stores instruction information for the pause processing of the data transfer; and
a register which stores information which indicates that the pause processing has been completed for all of the pipe regions.
12. The data transfer control device as defined in claim 1, comprising:
a register section including a plurality of transfer condition registers, transfer condition information on data transfer between each of the pipe regions and corresponding one of the endpoints being set in each of the transfer condition registers,
wherein the transfer controller automatically generates a transaction for each of the endpoints based on the transfer condition information set in each of the transfer condition registers, and automatically transfers data between each of the pipe regions and corresponding one of the endpoints.
13. The data transfer control device as defined in claim 7, comprising:
a register section including a plurality of transfer condition registers, transfer condition information on data transfer between each of the pipe regions and corresponding one of the endpoints being set in each of the transfer condition registers,
wherein the transfer controller automatically generates a transaction for each of the endpoints based on the transfer condition information set in each of the transfer condition registers, and automatically transfers data between each of the pipe regions and corresponding one of the endpoints.
14. The data transfer control device as defined in claim 1, comprising:
a state controller which controls a plurality of states including a state of a host operation in which the data transfer control device operates as a role of a host and a state of a peripheral operation in which the data transfer control device operates as a role of a peripheral,
wherein the transfer controller includes a host controller which transfers data as the host during the host operation and a peripheral controller which transfers data as the peripheral during the peripheral operation, and
wherein, during the host operation, the buffer controller allocates the pipe regions in the packet buffer, and the host controller transfers data between each of the allocated pipe regions and corresponding one of the endpoints.
15. The data transfer control device as defined in claim 7, comprising:
a state controller which controls a plurality of states including a state of a host operation in which the data transfer control device operates as a role of a host and a state of a peripheral operation in which the data transfer control device operates as a role of a peripheral,
wherein the transfer controller includes a host controller which transfers data as the host during the host operation and a peripheral controller which transfers data as the peripheral during the peripheral operation, and
wherein, during the host operation, the buffer controller allocates the pipe regions in the packet buffer, and the host controller transfers data between each of the allocated pipe regions and corresponding one of the endpoints.
16. The data transfer control device as defined in claim 1, which performs data transfer according to a Universal Serial Bus (USB) On-The-Go (OTG) standard.
17. The data transfer control device as defined in claim 7, which performs data transfer according to a Universal Serial Bus (USB) On-The-Go (OTG) standard.
18. An electronic instrument comprising:
the data transfer control device as defined in claim 1;
a device which performs one of output processing, fetch processing, and storage processing of data transferred through the data transfer control device and a bus; and
a processing section which controls data transfer of the data transfer control device.
19. An electronic instrument comprising:
the data transfer control device as defined in claim 7;
a device which performs one of output processing, fetch processing, and storage processing of data transferred through the data transfer control device and a bus; and
a processing section which controls data transfer of the data transfer control device.
20. A data transfer control method for data transfer through a bus, the data transfer control method comprising:
allocating a plurality of pipe regions in a packet buffer, and controlling access to the packet buffer, each of the pipe regions storing data transferred to or from corresponding one of endpoints;
controlling data transfer between each of the pipe regions and corresponding one of the endpoints;
storing pipe region numbers each of which is assigned to at least one of divided blocks, the divided blocks being obtained by dividing a memory region of the packet buffer, and generating a physical access address of the packet buffer based on the stored pipe region numbers, a pipe region number to which access is requested, and a relative access address of the pipe regions; and
performing reconstruction processing of the pipe regions by changing the pipe region number assigned to the divided block of the packet buffer, the reconstruction processing including at least one of processing of deleting the allocated pipe region, processing of adding a new pipe region, and processing of changing a size of the pipe region.
21. A data transfer control method for data transfer through a bus, the data transfer control method comprising:
allocating a plurality of pipe regions in a packet buffer, and controlling access to the packet buffer, each of the pipe regions storing data transferred to or from corresponding one of endpoints;
controlling data transfer between each of the pipe regions and corresponding one of the endpoints;
translating a logical access address of the packet buffer into a physical access address of the packet buffer;
performing reconstruction processing of the pipe regions by changing correspondence between the logical access address and the physical access address in the address translation, the reconstruction processing including at least one of processing of deleting the allocated pipe region, processing of adding a new pipe region, and processing of changing a size of the pipe region; and
changing the correspondence between the logical access address and the physical access address for a first pipe region allocated in the packet buffer before and after the reconstruction processing corresponding to a first endpoint so that the physical access address does not change even when the logical access address of the first pipe region changes.