1. A fork-lift reach truck having an extraction mast which is adapted to be displaced, by means of a mast drive, towards and away from a driving portion of the fork-lift truck on a horizontal guide, a load-carrying means which is mounted on a side shift, a side shift guide which is supported by the extraction mast in a height-adjustable way and is adapted to be actuated by means of a lifting and lowering drive, which guides the side shift in a laterally movable way, and a side shift drive, and an electric control and regulation device for the respective drives which is connected to operating members for the lifting and lowering modes, the mast extraction mode, and the side shift mode, characterized in that an analog sensor (30) detecting the position of the side shift (20) is provided the position signal of which is sent to the control and regulation device (34), and that the control and regulation device (34) is connected to a separate operating member for the side shift (20) or the operating member for the side shift is configured in such a way that actuating it causes the side shift (20) to be automatically moved to a predetermined position, preferably a middle position.
2. The fork-lift reach truck as claimed in claim 1, characterized in that the operating member (36) for the side shift (20) is configured as a set point transmitter which, in response to its displacement path or angle, generates a set point signal for the control and regulation device (34).
3. The fork-lift reach truck as claimed in claim 1, characterized in that the control and regulation device (34) sends a signal to the side shift drive (26) to move to the predetermined position when a signal for a retraction of the mast (12) is generated by the operating member (42) for the mast extraction andor a signal for the lowering of the load-carrying means (16) is generated by the operating member (44) for the lifting and lowering modes.
4. The fork-lift truck as claimed in claim 1, characterized in that the control and regulation device (34) is connected to an onboard computer (46) andor forms part thereof, the onboard computer (34) limits the traveling andor cornering speed of the fork-lift truck in conformity with stability criteria and the position signal of the sensor (30) is sent to the onboard computer (46) for a modification of the traveling speed of the fork-lift truck in dependence on the position of the side shift (20).
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device, comprising:
a semiconductor substrate having a main surface;
a memory cell region including a plurality of magnetoresistive elements formed over the main surface of the semiconductor substrate, and changing in electrical resistance according to the direction of magnetization, disposed therein, the magnetoresistive element including a magnetization fixed layer fixed in direction of magnetization, a magnetization free layer made variable indirection of magnetization, and a tunneling insulation layer interposed between the magnetization fixed layer and the magnetization free layer;
an interlayer insulation film disposed at the same layer as the magnetoresistive elements;
a peripheral circuit region disposed in the periphery of the memory cell region in plan view;
a plurality of first wires formed above the magnetoresistive elements, extending in the direction along the main surface, and coupled to the top surfaces of the magnetoresistive elements; and
a multilayer structure disposed in the peripheral circuit region so as to overlap a second wire formed of the same layer as the first wire in plan view, the multilayer structure comprising a layer equal in material to the magnetization free layer forming the magnetoresistive element, a layer equal in material to the tunneling insulation layer, and a layer equal in material to the magnetization fixed layer,
wherein the multilayer structure is disposed so as not to overlap both of a pair of the adjacent second wires in plan view in the peripheral circuit region.
2. The semiconductor device according to claim 1, wherein the multilayer structure extends along the second wire in the peripheral circuit region in plan view.
3. The semiconductor device according to claim 1, wherein the multilayer structure is divided into a plurality of small multilayer structures with respect to the direction along the second wire in the peripheral circuit region in plan view.
4. The semiconductor device according to claim 3, wherein the small multilayer structure is disposed in such a manner as not to overlap a coupling wire for electrically coupling the second wire and other circuits over the main surface in plan view.
5. The semiconductor device according to claim 1, wherein the multilayer structure is disposed smaller than the second wire in plan view.
6. The semiconductor device according to claim 1, wherein the multilayer structure is disposed in such a manner as to overlap the entire surface of the second wire in plan view in the peripheral circuit region.
7. The semiconductor device according to claim 6, wherein the multilayer structure is disposed larger than the second wire in plan view.
8. The semiconductor device according to claim 1, wherein the sum of occupancy rates of regions including the multilayer structures disposed therein relative to the whole of the peripheral circuit region in plan view is larger than the sum of occupancy rates of regions including the magnetoresistive elements disposed therein in the whole of the memory cell region.
9. The semiconductor device according to claim 1, comprising an additional multilayer structure having the same configuration as that of the multilayer structure at a position at which the second wire is not disposed in the peripheral circuit region in plan view.
10. A semiconductor device, comprising:
a semiconductor substrate having a main surface;
a memory cell region including a plurality of resistance recording elements formed over the main surface of the semiconductor substrate, and changing in electrical resistance according to the application of a voltage, disposed therein;
an interlayer insulation film disposed at the same layer as the resistance recording elements; and
a peripheral circuit region disposed in the periphery of the memory cell region in plan view,
the resistance recording element including a first metal electrode, an insulation film, and a second metal electrode stacked in this order,
the semiconductor device, comprising:
above the resistance recording elements, a plurality of first wires extending in the direction along the main surface, and coupled to the top surfaces of the resistance recording elements; and
in the peripheral circuit region, a multilayer structure of lamination of a layer equal in material to the first metal electrode forming the resistance recording element, a layer equal in material to the insulation film, and a layer equal in material to the second metal electrode, disposed in such a manner as to overlap a second wire formed of the same layer as the first wire in plan view,
the multilayer structure being disposed in such a manner as not to overlap both of a pair of the adjacent second wires in plan view in the peripheral circuit region.
11. A semiconductor device, comprising:
a semiconductor substrate having a main surface;
a memory cell region including a plurality of phase change recording elements formed over the main surface of the semiconductor substrate, and changing in electrical resistance according to the phase change, disposed therein;
an interlayer insulation film disposed at the same layer as the phase change recording elements; and
a peripheral circuit region disposed in the periphery of the memory cell region in plan view,
the phase change recording element including a first metal electrode, a phase change layer, and a second metal electrode stacked in this order,
the semiconductor device, comprising:
above the phase change recording elements, a plurality of first wires extending in the direction along the main surface, and coupled to the top surfaces of the phase change recording elements; and
in the peripheral circuit region, a multilayer structure of lamination of a layer equal in material to the first metal electrode forming the phase change recording element, a layer equal in material to the phase change layer, and a layer equal in material to the second metal electrode, disposed in such a manner as to overlap a second wire formed of the same layer as the first wire in plan view,
the multilayer structure being disposed in such a manner as not to overlap both of a pair of the adjacent second wires in plan view in the peripheral circuit region.