1. An electrostatic discharge (ESD)-triggered protection apparatus, comprising:
an ESD trigger circuit to sense an ESD pulse and to generate a switching pulse responsive to the ESD pulse;
an ESD discharge device communicatively coupled to the ESD trigger circuit and responsive to the switching pulse to transfer a current generated by the ESD pulse to ground, the ESD discharge device comprising a MOS power transistor; and
a VDD turn-on clamp communicatively coupled to the ESD discharge device to prevent the ESD discharge device from switching to a conduction state during a VDD power-on event the VDD turn-on clamp further comprising:
a VDD turn-on clamp transistor to prevent conduction of the MOS power transistor at times other than the occurrence of an ESD event, a current channel of the VDD turn-on clamp transistor coupled between a gate of the MOS power transistor and ground;
a pull-up resistor coupled between the VDD voltage rail and a gate of the VDD turn-on clamp transistor to bias the VDD turn-on clamp transistor to a conductive state at VDD power-on; and
a clamp release transistor to disable the VDD turn-on clamp transistor upon the occurrence of an ESD event, a current channel of the clamp release transistor coupled between the gate of the VDD turn-on clamp transistor and ground, a gate of the clamp release transistor coupled to the gate of the MOS power transistor to drive the clamp release transistor to conduction at an occurrence of an ESD event.
2. The ESD-triggered protection apparatus of claim 1, further comprising:
an ESD discharge timer communicatively coupled to the ESD discharge device to determine a conduction period associated with the ESD discharge device.
3. The ESD-triggered protection apparatus of claim 2, the ESD discharge timer further comprising:
a gate-to-body capacitance of the MOS power transistor; and
a timer resistor coupled between a gate of the MOS power transistor and ground, a resistance value of the timer resistor selected to obtain a time constant sufficient to substantially discharge energy associated with the ESD pulse as current flow through the MOS power transistor to ground.
4. The ESD-triggered protection apparatus of claim 3, the timer resistor implemented as a long, narrow conduction channel associated with an inverting buffer transistor.
5. The ESD-triggered protection apparatus of claim 1, further comprising:
at least one inverting buffer communicatively coupled between the ESD trigger circuit and the ESD discharge device to propagate the switching pulse from the ESD trigger circuit to the ESD discharge device.
6. The ESD-triggered protection apparatus of claim 5, the at least one inverting buffer further comprising:
first, second, and third inverters, each inverter comprising a PMOS transistor coupled to a VDD voltage rail and an NMOS transistor coupled to ground, the NMOS transistor associated with the third inverter having a long, narrow-width channel to provide resistance characteristics.
7. The ESD-triggered protection apparatus of claim 1, the ESD trigger circuit further comprising:
a trigger circuit resistor coupled to a VDD voltage rail; and
a trigger circuit capacitor in series with the trigger circuit resistor to a ground rail, the switching pulse to originate at a junction of the trigger circuit resistor and the trigger circuit capacitor responsive to the ESD pulse.
8. The ESD-triggered protection apparatus of claim 1, wherein
the metal oxide semiconductor (MOS) power transistor has a current channel with a width sufficient to transfer the current generated by the ESD pulse to ground.
9. An electrostatic discharge (ESD)-triggered protection apparatus, comprising:
an ESD trigger circuit to sense an ESD pulse and to generate a switching pulse responsive to the ESD pulse;
an ESD discharge device communicatively coupled to the ESD trigger circuit and responsive to the switching pulse to transfer a current generated by the ESD pulse to ground; and
a VDD glitch clamp communicatively coupled to the ESD trigger circuit to prevent a VDD transmit-induced switching pulse from propagating to the ESD discharge device and causing the ESD discharge device to conduct, the VDD glitch clamp further comprising:
a first VDD glitch clamp transistor, a current channel of the first VDD glitch clamp transistor communicatively coupled to a path traversed by the switching pulse;
a second VDD glitch clamp transistor, a current channel of the second VDD glitch clamp transistor coupled in series between the current channel of the first VDD glitch clamp transistor and a ground rail, the first and second VDD glitch clamp transistors to clamp the path traversed by the switching pulse to ground absent an ESD pulse occurrence;
a pull-up resistor coupled between a VDD voltage rail and a gate of the first VDD glitch clamp transistor;
a VDD glitch clamp capacitor coupled between the gate of the first VDD glitch clamp transistor and the ground rail to maintain the first VDD glitch clamp transistor in a conductive state during a transient power supply disruption; and
a capacitor associated with the ESD trigger circuit communicatively coupled to a gate of the second VDD glitch clamp transistor to maintain the second VDD glitch clamp transistor in a conductive state during the transient power supply disruption.
10. The ESD-triggered protection apparatus of claim 9, further comprising:
an ESD discharge timer communicatively coupled to the ESD discharge device to determine a conduction period associated with the ESD discharge device.
11. The ESD-triggered protection apparatus of claim 9, further including:
at least one inverting buffer communicatively coupled between the ESD trigger circuit and the ESD discharge device to propagate the switching pulse from the ESD trigger circuit to the ESD discharge device.
12. An electrostatic discharge (ESD)-triggered protection apparatus, comprising:
an ESD trigger circuit to sense an ESD pulse and to generate a switching pulse responsive to the ESD pulse;
an ESD discharge device communicatively coupled to the ESD trigger circuit and responsive to the switching pulse to transfer a current generated by the ESD pulse to ground;
at least one inverting buffer communicatively coupled between the ESD trigger circuit and the ESD discharge device to propagate the switching pulse from the ESD trigger circuit to the ESD discharge device;
an ESD discharge timer communicatively coupled to the ESD discharge device to determine a conduction period associated with the ESD discharge device;
a VDD turn-on clamp communicatively coupled to the ESD discharge device to prevent the ESD discharge device from switching to a conduction state during a VDD power-on event;
a VDD glitch clamp communicatively coupled to the ESD trigger circuit to prevent a VDD transmit-induced switching pulse from propagating to the ESD discharge device and causing the ESD discharge device to conduct, the VDD glitch clamp further comprising:
a first VDD glitch clamp transistor, a current channel of the first VDD glitch clamp transistor communicatively coupled to a path traversed by the switching pulse;
a second VDD glitch clamp transistor, a current channel of the second VDD glitch clamp transistor coupled in series between the current channel of the first VDD glitch clamp transistor and ground, the first and second VDD glitch clamp transistors to clamp the path traversed by the switching pulse to ground absent an ESD pulse occurrence;
a pull-up resistor coupled between a VDD voltage rail and a gate of the first VDD glitch clamp transistor;
a VDD glitch clamp capacitor coupled between the gate of the first VDD glitch clamp transistor and the ground rail to maintain the first VDD glitch clamp transistor in a conductive state during a transient power supply disruption; and
a capacitor associated with the ESD trigger circuit communicatively coupled to a gate of the second VDD glitch clamp transistor to maintain the second VDD glitch clamp transistor in a conductive state during a transient power supply disruption.
13. The ESD-triggered protection apparatus of claim 12, the VDD glitch clamp capacitor comprising a gate-to-source internal capacitance associated with the VDD turn-on clamp transistor.
14. The ESD-triggered protection apparatus of claim 12, the ESD trigger circuit further comprising:
a trigger circuit resistor coupled to a VDD voltage rail; and
a trigger circuit capacitor in series with the trigger circuit resistor to a ground rail, the switching pulse to originate at a junction of the trigger circuit resistor and the trigger circuit capacitor responsive to the ESD pulse.
15. The ESD-triggered protection apparatus of claim 12, the ESD discharge device further comprising:
a metal oxide semiconductor (MOS) power transistor having a current channel of width sufficient to transfer the current generated by the ESD pulse to ground.
16. The ESD-triggered protection apparatus of claim 12, the ESD discharge timer further comprising:
a gate-to-body capacitance of a MOS power transistor; and
a timer resistor coupled between a gate of the MOS power transistor and ground, a resistance value of the timer resistor selected to obtain a time constant sufficient to substantially discharge energy associated with the ESD pulse as current flow through the MOS power transistor to ground.
17. The ESD-triggered protection apparatus of claim 12, the VDD turn-on clamp further comprising:
a VDD turn-on clamp transistor to prevent conduction of a MOS power transistor of the ESD discharge device at times other than the occurrence of an ESD event, a current channel of the VDD turn-on clamp transistor coupled between a gate of the MOS power transistor and ground;
the pull-up resistor coupled between the VDD voltage rail and a gate of the VDD turn-on clamp transistor to bias the VDD turn-on clamp transistor to a conductive state at VDD power-on; and
a clamp release transistor to disable the VDD turn-on clamp transistor upon the occurrence of an ESD event, a current channel of the clamp release transistor coupled between the gate of the VDD turn-on clamp transistor and ground, a gate of the clamp release transistor coupled to the gate of the MOS power transistor to drive the clamp release transistor to conduction at an occurrence of an ESD event.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An antiglare mirror, comprising:
a first electrode layer;
a second electrode layer that is optically transparent;
a dichroic material sandwiched between the first and second electrodes layers and exhibiting a high optical absorption when the first and second electrode layers are biased at a first electrical bias state and a low optical absorption when the first and second electrode layers are biased at a second, different electrical bias state, wherein the dichroic material switches between the high optical absorption and the low optical absorption in less than 0.1 second; and
a control circuit coupled to the first and second electrode layers and operable to control electrical bias between the first and second electrode layers and thus optical absorption of the dichroic material.
2. The mirror as in claim 1, wherein the control circuit further comprises a sensor which causes the first electrical bias state to be applied when light received in the mirror is greater than a threshold intensity and causes the second electrical bias state to be applied when light received in the mirror is less than the threshold intensity.
3. The mirror as in claim 2, wherein the sensor comprises one or more light detectors which are assembled behind the metal coating to measure incident light.
4. The mirror as in claim 1, wherein the second electrode layer is made of ITO.
5. The mirror as in claim 4, further comprising an additional dielectric layer between the ITO layer and the dichroic material.
6. The mirror as in claim 1, wherein the dichroic material includes a dichroic liquid crystal mixture.
7. The mirror as in claim 1, wherein the dichroic material includes a dichroic dye.
8. The mirror as in claim 1, wherein the first electrode layer is at least partially optically reflective.
9. The mirror as in claim 1, wherein the first electrical bias state is a state where a voltage is applied to the dichroic material and the second electrical bias state is a state where no voltage is applied to the dichroic material.
10. The mirror as in claim 1, wherein the second electrical bias state is a state where a voltage is applied to the dichroic material and the first electrical bias state is a state where no voltage is applied to the dichroic material.
11. A pair of eye glasses, comprising:
a first electrode layer that is optically transparent;,
a second electrode layer that is optically transparent;
a dichroic material sandwiched between the first and second electrodes layers and exhibiting a high optical absorption when the first and second electrode layers are biased at a first electrical bias state and a low optical absorption when the first and second electrode layers are biased at a second, different electrical bias state; and
a control circuit coupled to the first and second electrode layers and operable to control electrical bias between the first and second electrode layers and thus optical absorption of the dichroic material.
12. The pair of eye glasses as in claim 11, wherein the control circuit further comprises a sensor which causes the first electrical bias state to be applied when light received in the mirror is greater than a threshold intensity and causes the second electrical bias state to be applied when light received in the mirror is less than the threshold intensity.
13. The pair of eye glasses as in claim 11, wherein the first and second electrode layers are made of ITO.
14. The pair of eye glasses as in claim 11, wherein the dichroic material includes a dichroic liquid crystal mixture.
15. The pair of eye glasses as in claim 11, wherein the dichroic material includes a dichroic dye.
16. The pair of eye glasses as in claim 11, wherein the first electrical bias state is a state where a voltage is applied to the dichroic material and the second electrical bias state is a state where no voltage is applied to the dichroic material.
17. The pair of eye glasses as in claim 11, wherein the dichroic material is operable to switch between the high optical absorption and the low optical absorption in less than 0.1 second.
18. An antiglare mirror, comprising:
a first electrode layer that is at least partially transparent and a second electrode layer that is at least partially transparent;
a dichroic material sandwiched between the first and second electrodes layers and exhibiting a high optical absorption when the first and second electrode layers are biased at a first electrical bias state and a low optical absorption when the first and second electrode layers are biased at a second, different electrical bias state;
a control circuit coupled to the first and second electrode layers and operable to control electrical bias between the first and second electrode layers and thus optical absorption of the dichroic material; and
a reflective layer positioned to receive light transmitted through the first and second electrodes and the dichroic material and reflect the received light back.
19. The mirror as in claim 18, wherein the dichroic material is operable to switch between the high optical absorption and the low optical absorption in less than 0.1 second.
20. The mirror as in claim 18, wherein the dichroic material includes a dichroic dye.