1. A semiconductor structure comprising a temperature control device and an optoelectronic device,
wherein said temperature control device includes:
a first metal semiconductor alloy region located on a substrate;
a p-doped semiconductor portion abutting said first metal semiconductor alloy region and located on said substrate;
an n-doped semiconductor portion abutting said first metal semiconductor alloy region located on said substrate; wherein said temperature control device is configured to pass current from said p-doped semiconductor portion, through said first metal semiconductor alloy region, and to said n-doped semiconductor portion or from said n-doped semiconductor portion, through said first metal semiconductor alloy region, and to said p-doped semiconductor portion, and
wherein said optoelectronic device includes a device that comprises a semiconductor material, configured to manipulate electromagnetic radiation, and is thermally coupled to said temperature control device.
2. The semiconductor structure of claim 1, wherein said optoelectronic device includes at least one of a laser, optical amplifier, an optical sensor, a waveguide, and a quantum well.
3. The semiconductor structure of claim 1, wherein said optoelectronic device includes a III-V compound semiconductor material.
4. The semiconductor structure of claim 1, further comprising a dielectric material portion comprising a dielectric material and vertically abutting a bottom surface of said p-doped semiconductor portion and a bottom surface of said n-doped semiconductor portion.
5. The semiconductor structure of claim 4, wherein said dielectric material is silicon oxide, and wherein said substrate includes a bottom semiconductor layer vertically abutting a bottom surface of said dielectric material portion.
6. The semiconductor structure of claim 4, further comprising a low dielectric constant (low-k) dielectric material portion laterally abutting said dielectric material portion, wherein said low-k dielectric material portion has a dielectric constant that is less than 3.0.
7. The semiconductor structure of claim 4, further comprising a cavity laterally abutting said dielectric material portion and having a dielectric constant that is substantially equal to 1.0.
8. The semiconductor structure of claim 1, wherein said p-doped semiconductor portion laterally abuts said n-doped semiconductor portion.
9. The semiconductor structure of claim 1, further comprising a substantially intrinsic semiconductor portion laterally abutting said p-doped semiconductor portion and said n-doped semiconductor portion and vertically abutting said first metal semiconductor alloy region, wherein said substantially intrinsic semiconductor portion has a resistivity greater than 1 Ohm-cm.
10. The semiconductor structure of claim 1, further comprising a semiconductor waveguide comprising a substantially intrinsic semiconductor material having the same composition as said p-doped semiconductor portion and said n-doped semiconductor portion except for dopant species and dopant concentration, and wherein said substantially intrinsic semiconductor material has a resistivity greater than 1 Ohm-cm.
11. The semiconductor structure of claim 1, wherein said temperature control device further comprises:
a second metal semiconductor alloy region vertically abutting said p-doped semiconductor portion;
a third metal semiconductor alloy region vertically abutting said n-doped semiconductor portion;
a first metal contact via abutting said second metal semiconductor alloy region; and
a second metal contact via abutting said third metal semiconductor alloy region.
12. The semiconductor structure of claim 11, further comprising a dielectric material portion comprising a dielectric material and having a first edge underlying a sub-portion of said p-doped semiconductor portion located between said first metal semiconductor region and said second metal semiconductor region and having a second edge underlying a sub-portion of said n-doped semiconductor portion located between said first metal semiconductor region and said third metal semiconductor region.
13. The semiconductor structure of claim 1, further comprising at least one compound semiconductor via vertically abutting said optoelectronic device and providing conduction of electrical current or transmission of light to or from said optoelectronic device.
14. A method of operating a semiconductor structure comprising a temperature control device and an optoelectronic device, said method including:
providing a temperature control device including a first metal semiconductor alloy region located on a substrate, a p-doped semiconductor portion abutting said first metal semiconductor alloy region and located on said substrate, and an n-doped semiconductor portion abutting said first metal semiconductor alloy region located on said substrate;
providing an optoelectronic device including a device that comprises a semiconductor material, configured to manipulate electromagnetic radiation, and is thermally coupled to said temperature control device; and
passing electrical current from said p-doped semiconductor portion, through said first metal semiconductor alloy region, and to said n-doped semiconductor portion or from said n-doped semiconductor portion, through said first metal semiconductor alloy region, and to said p-doped semiconductor portion, wherein heat is transferred in the direction of flow of majority charge carriers in said p-doped semiconductor portion and said n-doped semiconductor portion.
15. The method of claim 14, wherein said optoelectronic device overlies said first metal semiconductor alloy region.
16. The method of claim 14, further comprising:
monitoring performance of said optoelectronic device; and
adjusting a direction of said electrical current or magnitude of said electrical current to reduce deviation in said performance from a target performance level.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method comprising:
receiving location data indicative of a geographic position;
sending the location data to a server;
receiving traffic data for a plurality of parallel lanes based on the location data, wherein the traffic data for at least one of the parallel lanes is based on a combination of current traffic measurements and historic traffic measurements; and
displaying the traffic data for the plurality of parallel lanes.
2. The method of claim 1, wherein the traffic data includes a traffic value for each of the parallel lanes.
3. The method of claim 2, further comprising:
identifying a graphical indicator for the traffic value for each of the parallel lanes.
4. The method of claim 1, wherein the probe data includes real time data for only a first lane of the parallel lanes and historical data for both the first lane and a second lane of the parallel lanes.
5. The method of claim 4, wherein the historical data includes a ratio between historical traffic levels for the first lane and historical traffic levels for the second lane.
6. The method of claim 1, wherein the traffic data is received through a traffic message channel broadcast.
7. The method of claim 1, wherein the traffic data includes a road segment identification value.
8. The method of claim 1, wherein the plurality of parallel lanes includes an exit ramp lane and a through lane, a first traffic level of the traffic data corresponds to the exit ramp lane, and a second traffic level of the traffic data corresponds to the through lane.
9. The method of claim 1, wherein the plurality of parallel lanes includes a forked route.
10. The method of claim 1, where the traffic data includes at least two traffic levels.
11. The method of claim 1, wherein the plurality of parallel lanes have a common upstream road segment.
12. The method of claim 1, wherein the geographic position is a location of a mobile device traveling on one of the plurality of parallel lanes.
13. An apparatus comprising:
at least one processor; and
at least one memory including computer program code for one or more programs; the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to at least perform:
receiving location data indicative of a geographic position;
sending the location data to a server; and
receiving traffic data for a plurality of parallel lanes based on the location data, wherein the traffic data for at least one of the parallel lanes is based on a combination of current traffic measurements and historic traffic measurements.
14. The apparatus of claim 13, the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to at least perform:
generating data for display of the traffic data for the plurality of parallel lanes.
15. The apparatus of claim 13, wherein the traffic data includes a traffic value for each of the parallel lanes.
16. The apparatus of claim 13, wherein the probe data includes real time data for only a first lane of the parallel lanes and historical data for both the first lane and a second lane of the parallel lanes.
17. The apparatus of claim 13, wherein the historical data includes a ratio between historical traffic levels for the first lane and historical traffic levels for the second lane.
18. The apparatus of claim 13, wherein the plurality of parallel lanes includes an exit ramp lane and a through lane, a first traffic level of the traffic data corresponds to the exit ramp lane, and a second traffic level of the traffic data corresponds to the through lane.
19. A method comprising:
receiving location data indicative of a geographic position;
sending the location data to a server; and
receiving traffic data for a first lane and a second lane based on the location data, wherein the traffic data for the first lane is based on a combination of current traffic measurements and historic traffic measurements; and
generating a first graphical indicator for the traffic data for the first lane and a second graphical indicator for the traffic data for the second lane.
20. The method of claim 19, wherein the first lane and the second lane form a forked route.