1. A method of reclaiming a well completion brine comprising the steps of:
a. mixing the brine containing metal impurities with an organic chelant for a time sufficient for the chelant to complex a metal and form a complexed metal precipitate; and
b. removing the complexed metal precipitate from the brine wherein the metal impurities contain iron and further wherein the complexed metal precipitate contains iron.
2. The method of claim 1, wherein the organic chelant contains up to about 120 carbon atoms and further contains at least one functional group selected from the group consisting of \u2014CO2H or \u2014PO(OH)R20 or a salt or ester thereof, \u2014C(O)\u2014, \u2014OE, \u2014SE, \u2014N\u2550C(R2)R3, EO\u2014N\u2550C(R2)R3, \u2014N(R2)R3, and a \u2014N(C(O)R1)R2 group, optionally substituted with a \u2014COOH or \u2014PO(OH)R20 or a salt or ester thereof or \u2014SE or \u2014OE group, wherein R2 and R3 are independently selected from E or forms, with nitrogen, phosphorous, oxygen or sulfur, a heterocyclic ring; E is R1 or \u2014H; R1 is a C1\u2013C30 alkyl or aralkyl group or a derivative thereof; and R20 is either \u2014OH or R1.
3. The method of claim 2, wherein the organic chelant is further substituted with at least one group selected from \u2014CO2H or \u2014PO(OH)R20 or a salt or ester thereof, \u2014C(O)\u2014, \u2014OE, \u2014SE, \u2014N\u2550C(R2)R3, EO\u2014N\u2550C(R2)R3, \u2014P(R2)R3, \u2014POR2R3, \u2014PO3, \u2014OPO3, \u2014SO3, \u2014OSO3, \u2014NO2, \u2014N(R2)R3 or \u2014N(C(O)R1)R2.
4. The method of claim 3, wherein the organic chelant is a dioxime having the structural formula:
R2C(\u2550N\u2014OE)(CnH2nYw)x(R6)yYw(CnH2n)zC(\u2550N\u2014OE)R3
or a derivative thereof;
wherein R2 and R3 are independently selected from R1, \u2014(CH2)sOE, \u2014(CH2)sSE or \u2014(CH2)sCOOH or \u2014CH2)sPO(OH)R20 or a salt or ester thereof, R1 is \u2014H or a C1\u2013C30 alkyl or aralkyl group or derivative thereof, R6 is CnH2n or a derivative thereof, E is R1 or \u2014H; Y is \u2014O, \u2014S, \u2014P or \u2014N; s is 1 to 4, n is 0 to 5, w is 0 or 1 and x, y and z are independently 0 to 5.
5. The method of claim 2, further comprising mixing the brine with an oxidizer.
6. The method of claim 5, wherein the oxidizer is a slow reacting oxidizer.
7. The method of claim 6, wherein the oxidizer is calcium peroxide or magnesium peroxide.
8. The method of claim 7, wherein the organic chelant is benzoic acid or a salt or ester thereof.
9. The method of claim 2, wherein the functional group is \u2014COOH or a salt or ester thereof.
10. The method of claim 9, wherein the organic chelant is benzoic acid or a salt or ester thereof.
11. The method of claim 9, wherein the organic chelant is further substituted with at least one group selected from \u2014OE, \u2014SE, \u2014P(R2)R3, \u2014POR2R3, \u2014PO3, \u2014OPO3, \u2014SO3, \u2014OSO3, \u2014NO2, \u2014N\u2550C(R2)R3, EO\u2014N\u2550C(R2)R3, \u2014N(R2)R3, \u2014N(CH2)2 and \u2014N(C(O)R1)R2 optionally substituted with a \u2014COOH or \u2014PO(OH)R20 group or a salt or ester thereof or with an \u2014OE or _SE group.
12. The method of claim 11, wherein the organic chelant further contains the functional group \u2014NR2R3 optionally substituted with a \u2014COOH or \u2014PO(OH)R20 group or a salt or ester thereof or with an \u2014OE or \u2014SE group.
13. The method of claim 12, wherein the organic chelant is nitrilotriacetic acid or a salt or ester thereof.
14. The method of claim 11, wherein the organic chelant is an ethylene diamine type of the structural formula:
(F)(R9)A(U)k(V)t(CnH2n)A(R10)(R11)\u2003\u2003(I)
or a derivative thereof
wherein A is nitrogen or phosphorus; R8, R9, R10 and R11 are independently \u2014(CH2)xCOOH or \u2014(CH2)xPO(OH)R20 or a salt or ester thereof, \u2014(CH2)xOE or (CH2)xSE or a derivative thereof; R5 is \u2014H or a C1\u2013C30 alkyl or aralkyl group or derivative thereof; R14 is R5 or R8; F is \u2014(CH2)xCOOH or \u2014(CH2)xPO(OH)R20 or a salt or ester thereof, \u2014OE, \u2014SE, \u2014(CH2)xSE or \u2014(CH2)xOE or a derivative thereof; U is \u2014(CH2CONR14\u2014)x; V is \u2014(CnH2nAR8\u2014); n is 1 to 15; x is 1 to 4; and k, z and t are independently 0 to 2.
15. The method of claim 14, wherein the organic chelant is selected from the group consisting of ethylene diamine tetra acetic acid; hydroxyethylenediamine triacetic; O,O\u2032-bis(2-aminoethyl)ethyleneglycol-N,N,N\u2032,N\u2032-tetraacetic acid; N-(glycylglycyl)-1,2-diaminoethane-N\u2032,N\u2032,N\u2033,N\u2033-tetraacetic acid.
16. The method of claim 9, wherein the organic chelant further contains the functional group \u2014N(COR1)R2 group optionally substituted with a \u2014COOH or \u2014PO(OH)R20 group or a salt or ester thereof or with an \u2014OE or SE group.
17. The method of claim 16, wherein the organic chelant contains from ten to one hundred twenty carbon atoms.
18. The method of claim 17, wherein the organic chelant contains a counter ion selected from the group consisting of ionic forms of sodium, potassium, cesium, ammonium, monoethanolamine, diethanolamine, triethanolamine, N-propylamine, isopropylamine, 2-amino-2-methyl-1,3-propane diol, 2-amino-2-methyl-1-propanol, 2-amino-2-ethyl-1,3-propane diol, tris(hydroxymethyl)aminomethane, group II metals, and a Group 3\u20137 transition metal.
19. The method of claim 9, wherein the organic chelant is substituted with at least one \u2014OE, \u2014SE, \u2014POR2R3, \u2014PO3, \u2014OPO3, \u2014SO3, or \u2014OSO3 group.
20. The method of claim 19, wherein the organic chelant is substituted with an \u2014OE group.
21. The method of claim 20, wherein the organic chelant is zinc di-(12-hydroxy-9-octadecenoate).
22. The method of claim 9, wherein the organic chelant is substituted with a \u2014P(R2)R3 or \u2014POR2R3 group.
23. The method of claim 22, wherein the organic chelant is of the formula (HOOCCH2)2PCH2CH2P(CH2COOH)2 or a salt or ester thereof.
24. The method of claim 8, wherein the organic chelant is selected from the group consisting of benzoic acid; benzene-1,2-dicarboxylic acid; benzene-1,3,5-tricarboxylic acid; nonyl-1,3-dicarboxylic acid; and 1-hydroxy-2-napthoic acid and salts thereof.
25. The method of claim 2, wherein the organic chelant contains at least one \u2014N(R2)R3, \u2014N\u2550C(R2)R3, EO\u2014N\u2550C(R2)R3 or a \u2014N(C(O)R1)R2 group wherein R2 and R3 independently may be substituted with a \u2014COOH, \u2014PO(OH)R20, \u2014SE or \u2014OE group or a salt or ester thereof.
26. The method of claim 25, wherein the organic chelant is N,N\u2032-dimethyl-N,N\u2032-dilauroylethylenediamine or a salt thereof.
27. The method of claim 25, wherein the organic chelant is 1,2-diaminobenzene or a salt thereof.
28. The method of claim 25, wherein the organic chelant is iminobis (methylenephosphonic acid) or a salt or ester thereof.
29. The method of claim 25, wherein the organic chelant is further substituted with at least one group selected from \u2014OE, \u2014SE, \u2014PO3, \u2014OPO3, \u2014SO3, \u2014OSO3, or \u2014NO2.
30. The method of claim 29, wherein the organic chelant is substituted with an \u2014OE group.
31. The method of claim 30, wherein the organic chelant is 8-hydroxy quinoline or a salt thereof.
32. The method of claim 30, wherein the organic chelant is substituted with a \u2014SO3 or a \u2014OSO3 group.
33. The method of claim 25, wherein the organic chelant is substituted with a \u2014SO3 or a \u2014OSO3 group.
34. The method of claim 33, wherein the organic chelant is 1-aminobenzene-2-sulfonic acid or a salt thereof.
35. The method of claim 25, wherein the organic chelant is a nitrogen, phosphorous, oxygen or sulfur containing heterocyclic ring.
36. The method of claim 35, wherein the organic chelant is porphine or derivatives thereof or salts thereof.
37. The method of claim 25, wherein the organic chelant is selected from the group consisting of ethylenediaminetetraacetic acid, 1,2-dimethylethylenedinitrilotetraacetic acid; DL-1-alkylethylenedinitrilotetraacetic acid N,N\u2032-diamide; 1,2-dimethylethylenedinitrilotetraacetic acid N,N\u2032-diamide; 1,2-phenylenedinitrilotetraacetic acid; N,N-dimethyl-2-aminophenol; and 4-phenyl-8-mercaptoquinoline and salts thereof.
38. The method of claim 2, wherein the functional group is \u2014OE or \u2014SE.
39. The method of claim 38, wherein the organic chelant is N-hydroxy-N-nitrosobenzenamine or a salt thereof.
40. The method of claim 38, wherein the organic chelant further contains at least one group selected from \u2014PO3, \u2014OPO3, \u2014SO3, \u2014OSO3, or \u2014NO2.
41. The method of claim 40, wherein the organic chelant contains a \u2014SO3 or \u2014OSO3 group.
42. The method of claim 41, wherein the organic chelant is 1-hydroxybenzene-2-sulfonic acid or a salt thereof.
43. The method of claim 38, wherein the organic chelant contains a \u2014PO3 or \u2014OPO3 group.
44. The method of claim 40, wherein the organic chelant is 4-nitro-1,2-dihydroxy benzene or a salt thereof.
45. The method of claim 2, wherein the organic chelant is a diketone having the structural formula:
R12C(O)(CnH2nYw)x(R6)yYw(CnH2n)zC(O)R13
or derivative thereof
wherein R12 and R13 are independently \u2014H or a C1\u2013C30 alkyl or aralkyl group optionally substituted with a \u2014COOH or \u2014PO(OH)R20 or a salt or ester thereof, \u2014N(R2)R3, \u2014SE or \u2014OE group; R6 is CnH2n or a derivative thereof; Y is \u2014O, \u2014S, \u2014P or \u2014N; n is 1 to 30, w is 0 or 1, and x, y and z are independently 0 to 5.
46. The method of claim 45, wherein the organic chelant is pentane-2,4-dione or octadecane-2,4-dione.
47. The method of claim 4, wherein the organic chelant is 2,3-butanedionedioxime.
48. The method of claim 1, further comprising mixing the brine with an oxidizer.
49. The method of claim 48, wherein the oxidizer is a slow reacting oxidizer.
50. The method of claim 1, further comprising adding to the brine an absorbent or defoamer.
51. The method of claim 50, wherein the absorbent is activated carbon.
52. The method of claim 48, further comprising adding to the brine an absorbent or defoamer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. Structure for a high voltage device of the type which comprises at least a semiconductor substrate being covered by an epitaxial layer of a first type of conductivity, wherein a plurality of column structures are realized, which column structures comprise high aspect ratio deep trenches, said epitaxial layer being in turn covered by an active surface area wherein said high voltage device is realized, wherein each of the column structures comprises at least an external portion being in turn realized by a silicon epitaxial layer of a second type of conductivity, opposed than said first type of conductivity and having a dopant charge which counterbalances the dopant charge being in said epitaxial layer outside said column structures, as well as a dielectric filling portion which is realized inside said external portion in order to completely fill said deep trench.
2. Structure for a high voltage device according to claim 1, wherein said epitaxial layer of said external portion is U-shaped and extends both on the wall and on the bottom of a corresponding column structure.
3. Structure for a high voltage device according to claim 2, wherein said external portion has a dopant concentration with a constant concentration dopant profile and with a transition zone towards said epitaxial layer outside said column structures having a smaller size than a thickness of a silicon epitaxial layer of said external portion.
4. Structure for a high voltage device according to claim 2, wherein said external portion has a dopant concentration with a growing dopant profile towards an interface with said epitaxial layer outside said column structures.
5. Structure for a high voltage device according to claim 4, wherein said external portion has a dopant concentration with a substantially constant concentration dopant profile.
6. Structure for a high voltage device according to claim 4, wherein said external portion has a dopant concentration with a variable concentration profile having a maximum near said interface with said epitaxial layer.
7. Structure for a high voltage device according to claim 2, wherein the thickness of said external portion is constant along its whole U-shaped profile.
8. Structure for a high voltage device according to claim 1, wherein said column structures have a ratio between width and height less than 320.
9. Structure for a high voltage device according to claim 1, wherein said column structures realize a first active area of said high voltage device and in that said high voltage device comprises at least a second active area which is realized in said active surface area and has at least one fastening zone with said first active area.
10. Structure for a high voltage device according to claim 9, wherein said first active area is fastened in correspondence with said fastening zone to a conduction portion of said first active area.
11. Structure for a high voltage device according to claim 9, wherein said conduction portion of said first active area is an external portion of said column structures.
12. Structure for a high voltage device according to claim 8, wherein said high voltage device is a MOS transistor of the Multi Drain type and in that said first active area is a drain area comprising said epitaxial layer and said column structures and in that said second active area is a body area.
13. Structure for a high voltage device according to claim 12, wherein said high voltage device comprises, in said active surface area, a plurality of body wells of said second type of conductivity, inside which corresponding plurality of source wells of said first type of conductivity are realized, as well as a plurality of gate structures, being realized between consecutive pairs of column structures, above a channel region being define in said epitaxial layer between said body wells and in contact with said source wells.
14. Structure for a high voltage device according to claim 13, it further comprising a capping layer, being realized on said high voltage device and in particular covering said gate structures.
15. Structure for a high voltage device according to claim 13, wherein said gate structures are chosen between planar type and trench gate type structures.
16. Structure for a high voltage device according to claim 13, it further comprising contact surface structures being chosen between microtrench type or conventional structures.
17. Structure for a high voltage device according to claim 8, wherein said column structures have a same periodicity with respect to said second active areas.
18. Structure for a high voltage device according to claim 1, wherein each of said column structures has a width between about 1.5 and 4 um, for example about 2 um and a height between about 10 and 70 um, for example about 30 um.
19. Structure for a high voltage device according to claim 1, wherein said external portion has a dopant concentration between about 1e15 and 1e17, for example about 1e16 atcm3 and said epitaxial layer has a dopant concentration between about 5e14 and 5e16, for example about 5e15.
20. Structure for a high voltage device according to claim 1, wherein said column structures have a distance between about 2 um and 8 um, for example about 4 um.
21. Structure for a high voltage device according to claim 1, wherein said column structures extend down to said semiconductor substrate.
22. Structure for a high voltage device according to claim 1, wherein said column structures extend down to a prefixed distance from said semiconductor substrate.
23. Structure for a high voltage device according to claim 1, wherein said high voltage device is chosen between a MOS transistor, a diode and an IGBT device.
24. Integration process of a structure for a high voltage device of the type which comprises the steps of:
realizing a semiconductor substrate having a first conductivity type;
epitaxially growing on said semiconductor substrate an epitaxial layer having said first conductivity type; and
realizing in said epitaxial layer at least one deep trench having a high aspect ratio in order to realize at least one column structure in said epitaxial layer;
an epitaxial growing step within said trench of a silicon layer being doped and having a second conductivity type, opposed than said first conductivity type and having a dopant charge which counterbalances a dopant charge being in said epitaxial layer outside said column structures and
a filling step of said trench by means of a filling dielectric layer in order to realize a filling portion of said at least one column structure.
25. Integration process according to claim 24, wherein said epitaxial growing step within said trench grows said silicon layer at least on the walls and on the bottom of said trench thus realizing an U-shaped external portion of said at least one column structure.
26. Integration process according to claim 24, wherein said epitaxial growing steps of said epitaxial layer on said semiconductor substrate and of said epitaxial layer within said trench are realized with a limited thermal budget and with a process maximum temperature less than 1100\xb0 C.
27. Integration process according to claim 26, wherein said epitaxial growing steps realize said epitaxial layer within said trench with a dopant concentration comprised between about 1e15 and 1e17, for example about 1e16 atcm3, and said epitaxial layer on said semiconductor substrate with a dopant concentration comprised between about 5e 14 and 5e16, for example about 5e15.
28. Integration process according to claim 24, wherein said column structures realize a first active area of said high voltage device and in that if further comprises a step of realizing, in an active surface area of said structure, at least one second active area which has at least one fastening zone with said first active area.
29. Integration process according to claim 28, further comprising integrating a MOS transistor of the multi-drain type, by realizing, as the first active area, a drain area which comprises said epitaxial layer and said column structures and, as the second active area, a body area.
30. Integration process according to claim 28, further comprising integrating a diode by realizing, as the first active area, a cathode area and, as the second active area, an anode area.
31. A structure, comprising:
a semiconductor layer having a first conductivity;
a first semiconductor region extending into the semiconductor layer and having a second conductivity; and
a first insulator region extending into the semiconductor region.
32. The structure of claim 31 wherein the semiconductor layer comprises an epitaxial layer.
33. The structure of claim 31 wherein the first conductivity comprises an N-type conductivity.
34. The structure of claim 31 wherein the semiconductor region comprises an epitaxial region.
35. The structure of claim 31 wherein the second conductivity comprises a P-type conductivity.
36. The structure of claim 31 wherein the insulator region comprises an oxide.
37. The structure of claim 31 wherein:
the semiconductor layer has a layer surface;
the semiconductor region extends into the semiconductor layer from an opening in the layer surface, and has a region surface; and
the insulator region extends into the semiconductor region from an opening in the region surface.
38. The structure of claim 31, further comprising:
wherein the semiconductor layer has a surface and forms a drain;
a body region of the second conductivity disposed in the semiconductor layer adjacent to the semiconductor region and the surface;
a source region of the first conductivity disposed in the body region adjacent to the surface;
a gate insulator disposed over the body region; and
a gate disposed over the gate insulator.
39. The structure of claim 31, further comprising:
wherein the semiconductor layer has a surface and forms a drain;
a body region of the second conductivity disposed in the semiconductor layer and adjacent to the semiconductor region and the surface;
a body extension region of the second conductivity disposed in the semiconductor region adjacent to the body region;
a source region of the first conductivity disposed in the body region adjacent to the surface;
a gate insulator disposed over the body region; and
a gate disposed over the gate insulator.
40. The structure of claim 31, further comprising:
wherein the semiconductor layer has a surface and forms a drain;
a body region of the second conductivity disposed in the semiconductor layer and adjacent to the semiconductor region and the surface;
a body-extension region of the second conductivity disposed in the semiconductor region adjacent to the body region;
a source region of the first conductivity disposed in the body region adjacent to the surface;
a gate insulator disposed over the body region;
a gate disposed over the gate insulator; and
a source contact region disposed over the surface and adjacent to the body-extension and source regions.
41. The structure of claim 31 wherein:
the semiconductor layer has a doping concentration of approximately between 5\xd71014 and 5\xd71016 atomscm3; and
the semiconductor region has a doping concentration of approximately between 1\xd71015 and 1\xd71017 atomscm3.
42. The structure of claim 31 wherein:
the semiconductor layer has a doping concentration of approximately 5\xd71015 atomscm3; and
the semiconductor region has a doping concentration of approximately 1\xd71016 atomscm3.
43. The structure of claim 31 wherein:
the semiconductor layer comprises a surface; and
the semiconductor region has a height from the surface of between approximately 10 and 70 \u03bcm.
44. The structure of claim 31 wherein:
the semiconductor layer comprises a surface; and
the semiconductor region has a height from the surface of approximately 30 \u03bcm.
45. The structure of claim 31 wherein the semiconductor region has a width of between approximately 1.5 and 4 \u03bcm.
46. The structure of claim 31 wherein the semiconductor region has a width of approximately 2 \u03bcm.
47. The structure of claim 31, further comprising:
a second semiconductor region extending into the semiconductor layer and having a second conductivity; and
a second insulator region extending into the second semiconductor region.
48. The structure of claim 47, further comprising:
wherein the semiconductor layer has a surface and forms a drain;
a first body region of the second conductivity disposed in the semiconductor layer adjacent to the first semiconductor region and the surface;
a first source region of the first conductivity disposed in the first body region adjacent to the surface;
a first gate insulator disposed over the first body region;
a first gate disposed over the gate insulator;
a second body region of the second conductivity disposed in the semiconductor layer adjacent to the second semiconductor region and the surface;
a second source region of the first conductivity disposed in the second body region adjacent to the surface;
a second gate insulator disposed over the second body region; and
a second gate disposed over the second gate insulator.
49. The structure of claim 47 wherein the first and second semiconductor regions are spaced apart by approximately 2 to 8 \u03bcm.
50. The structure of claim 47 wherein the first and second semiconductor regions are spaced apart by approximately 4 \u03bcm.
51. The structure of claim 47 wherein the first and second insulator regions are spaced apart by approximately 2.5 to 12 \u03bcm.
52. The structure of claim 47 wherein the first and second insulator regions are spaced apart by approximately 6 \u03bcm.
53. The structure of claim 31, further comprising:
wherein the semiconductor layer has a surface and forms a drain;
a first body region of the second conductivity disposed in the semiconductor layer adjacent to the semiconductor region and the surface;
a first source region of the first conductivity disposed in the first body region adjacent to the surface;
a first gate insulator disposed over the first body region;
a first gate disposed over the first gate insulator;
a second body region of the second conductivity disposed in the semiconductor layer adjacent to the first semiconductor region and the surface;
a second source region of the first conductivity disposed in the second body region adjacent to the surface;
a second gate insulator disposed over the second body region; and
a second gate disposed over the second gate insulator.
54. The structure of claim 31, further comprising:
wherein the semiconductor layer has a surface and forms a drain;
a first body region of the second conductivity disposed in the semiconductor layer adjacent to the semiconductor region and the surface;
a first body-extension region of the second conductivity disposed in the semiconductor region adjacent to the first body region;
a first source region of the first conductivity disposed in the first body region adjacent to the surface;
a first gate insulator disposed over the first body region;
a first gate disposed over the first gate insulator;
a second body region of the second conductivity disposed in the semiconductor layer adjacent to the first semiconductor region and the surface;
a second body-extension region of the second conductivity disposed in the semiconductor region adjacent to the second body region;
a second source region of the first conductivity disposed in the second body region adjacent to the surface;
a second gate insulator disposed over the second body region; and
a second gate disposed over the second gate insulator.
55. The semiconductor structure of claim 31, further comprising a doping transition region disposed between the semiconductor layer and the first semiconductor region.
56. The semiconductor structure of claim 31 wherein the first semiconductor region has an approximately constant doping profile between the semiconductor layer and the first insulator region.
57. The semiconductor structure of claim 31 wherein the first semiconductor region has a varying doping profile between the semiconductor layer and the first insulator region.
58. An integrated circuit, comprising:
a semiconductor layer having a first conductivity; and
an electronic device, comprising:
a first semiconductor region extending into the semiconductor layer and having a second conductivity; and
a first insulator region extending into the semiconductor region.
59. A system, comprising:
a first integrated circuit, comprising:
a semiconductor layer having a first conductivity; and
an electronic device, comprising:
a first semiconductor region extending into the semiconductor layer and having a second conductivity; and
a first insulator region extending into the semiconductor region; and
a second integrated circuit coupled to the first integrated circuit.
60. The system of claim 59 wherein the first and second integrated circuits are disposed on a same die.
61. The system of claim 59 wherein the first and second integrated circuits are disposed on respective dies.
62. The system of claim 59 wherein the second integrated circuit comprises a controller.
63. A method, comprising:
forming a first trench in a first semiconductor layer having a first conductivity;
lining a wall of the first trench with a second semiconductor layer having a second conductivity; and
forming a first insulator region in the lined first trench.
64. The method of claim 63, further comprising epitaxially growing the first semiconductor layer over a substrate.
65. The method of claim 63, further comprising epitaxially growing the second semiconductor layer over the first semiconductor layer.
66. The method of claim 63, further comprising:
forming a body region of the second conductivity in the first semiconductor layer adjacent to the trench;
forming a source region of the first conductivity in the body region;
forming a gate insulator over the body region; and
forming a gate over the gate insulator.
67. The method of claim 63, further comprising:
forming a body region of the second conductivity in the first semiconductor layer adjacent to the trench; and
forming a body-region extension of the second conductivity in the second semiconductor layer adjacent to the body region.
68. The method of claim 63, further comprising forming a body region of the second conductivity in the first and second semiconductor layers adjacent to a surface of the first semiconductor layer.
69. The method of claim 63, further comprising:
forming a second trench in the first semiconductor layer;
lining a wall of the second trench with a third semiconductor layer having the second conductivity; and
forming a second insulator region in the lined second trench.
70. The method of claim 63, further comprising:
wherein lining the wall of the first trench comprises lining the wall of the first trench with a first portion of the second semiconductor layer;
forming a second trench in the first semiconductor layer;
lining a wall of the second trench with a second portion of the second semiconductor layer; and
forming a second insulator region in the lined second trench.