1. A method of controlling a variable speed wind turbine generator connected to a power grid and comprising means for controlling the generator speed, said method:
measuring the frequency f of the power grid,
controlling the speed of the generator for optimizing the power delivered to the power grid, and
setting limits for the generator speed,
wherein the setting of the limits for the generator speed is performed in dependency of the measured frequency of the power grid.
2. The method of claim 1, wherein the dependency is set as follows:
a) whenever the measured frequency is within predetermined limits, a set of normal, fixed limits for the generator speed is imposed, and
b) whenever the measured frequency is outside said predetermined limits, the speed limits for the generator are adjusted relative to said fixed limits.
3. The method of claim 2, wherein the dependency, whenever the measured frequency is outside said predetermined limits, is an adjustment of the upper and lower speed limits with the same percentage as the frequency deviation \u0394f of the grid frequency from the nominal grid frequency.
4. The method of claim 2, wherein said predetermined limits are provided as a percentage of deviation from the nominal frequency.
5. The method of claim 4, wherein said percentage of deviation is \xb11%.
6. The method of claim 2, wherein the set of normal, fixed limits for the generator speed are set to provide an interval surrounding the synchronous speed at nominal frequency.
7. The method of claim 1, wherein the generator speed is further limited by a fixed maximum generator speed.
8. The method of claim 1, wherein the generator is disconnected from the power grid whenever the grid frequency exceed predetermined limits.
9. The method of claim 1, wherein the generator is disconnected whenever the grid frequency deviates more than a predetermined percentage from the nominal frequency.
10. The method of claim 4, wherein said percentage of deviation is \xb16%.
11. The method of claim 8, wherein the predetermined limits are a certain percentage deviation from the nominal frequency.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor storage device comprising:
a nonvolatile semiconductor memory; and
a controller coupled to the nonvolatile semiconductor memory, including:
a CPU,
a ROM in which a first firmware is stored, and
a RAM on which the first firmware is loaded to be executed by the CPU,
wherein the controller further includes:
a transfer section which receives, from an outside of the storage device, a command including modifying firmware and an interrupt vector having address information indicating an address on the RAM, and which writes the modifying firmware and the interrupt vector into the nonvolatile semiconductor memory; and
a load section which activates the modifying firmware stored in the nonvolatile semiconductor memory onto the RAM in accordance with the address information of the interrupt vector stored in the nonvolatile semiconductor memory to modify the first firmware.
2. The semiconductor storage device according to claim 1, wherein the nonvolatile semiconductor memory is a NAND flash memory having a plurality of data blocks and at least a management block area.
3. The semiconductor storage device according to claim 2, wherein the modifying firmware and the interrupt vector are stored into the management block area of the NAND flash memory.
4. The semiconductor storage device according to claim 1, wherein the load section activates the modifying firmware in response to a transfer trigger signal detected by the controller.
5. The semiconductor storage device according to claim 2, wherein the management block area has a card information structure page and a plurality of management pages.
6. The semiconductor storage device according to claim 2, wherein the NAND flash memory has an address conversion table in which a physical block address is in correspondence with a virtual physical block address and a virtual logical block address.
7. The semiconductor storage device according to claim 3, wherein the modifying firmware and the interrupt vector are written in the management block area in a lump.
8. The semiconductor storage device according to claim 3, wherein the modifying firmware and the interrupt vector are written in a block in the management block area which has the smallest number of ECC errors.
9. The semiconductor storage device according to claim 1, wherein the first firmware has a function of executing conversion between an address in a first semiconductor memory having a first erase block size assumed by a host and an address in the nonvolatile semiconductor memory having a second erase block size which is different from the first erase block size.
10. The semiconductor storage device according to claim 9, wherein the second erase block size is greater than the first erase block size.
11. The semiconductor storage device according to claim 1, wherein a first page buffer assumed by a host and a second page buffer in the nonvolatile semiconductor memory have different capacities.
12. The semiconductor storage device according to claim 11, wherein the capacity of the second page buffer is greater than that of the first page buffer.
13. The semiconductor storage device according to claim 1, wherein the modifying firmware and the interrupt vector further have at least one of information required to identify the modifying firmware or interrupt vector, information required to identify one or more modules to be modified, information required to identify one or more modules not to be modified, and information indicating a version number and the type of the modification.
14. The semiconductor storage device according to claim 2, wherein when the modifying firmware obtained is a revised version, the transfer section overwrites the corresponding modifying firmware in the management block area with the revised version.
15. The semiconductor storage device according to claim 2, wherein when the modifying firmware obtained is new, the transfer section writes the new modifying firmware in an unused area of the management block area.
16. The semiconductor storage device according to claim 14, wherein the transfer section writes the interrupt vector in the management block area as well as the modifying firmware.
17. The semiconductor storage device according to claim 15, wherein the transfer section writes the interrupt vector in the management block area as well as the modifying firmware.
18. The semiconductor storage device according to claim 1, wherein the modifying firmware is protocol conversion firmware.
19. The semiconductor storage device according to claim 1, wherein the modifying firmware is a CODEC firmware.
20. The semiconductor storage device according to claim 13, wherein the modification is an addition or a subtraction.