1. An integrated circuit wafer comprising a multiplicity of dice, the dice each including a multiplicity of integrated circuits and a plurality of contact pads that are exposed through contact pad openings formed in a top wafer fabrication passivation layer that constitutes an uppermost inorganic passivation layer formed on the wafer, the wafer further including:
a patterned copper layer that extends over the top surface of the top wafer fabrication passivation layer, wherein the patterned copper layer is electrically coupled to at least some of the contact pads through the contact pad openings;
a first titanium metallization layer that overlies at least portions of the patterned copper layer;
a first aluminum metallization layer that overlies at least portions of the first titanium metallization layer;
an electrically insulating organic protective layer that overlies the first aluminum metallization layer and the top wafer fabrication passivation layer, there being a plurality of contact openings in the protective layer; and
a plurality of underbump metallization stacks, each underbump metallization stack being electrically connected to the first aluminum metallization layer through an associated contact opening in the protective layer, wherein peripheral portions of the underbump metallization stacks extend over at least some adjacent portions of the protective layer.
2. An integrated circuit wafer as recited in claim 1 further comprising a plurality of solder bumps, each solder bump being adhered to an associated underbump metallization stack.
3. A wafer as recited in claim 1 wherein the underbump metallization stacks each include:
a second aluminum layer in contact with the first aluminum layer;
a nickel vanadium layer that overlies the second aluminum layer; and
a second copper layer that overlies the nickel vanadium layer; and
wherein peripheral portions of each of the layers in the underbump metallization stack extend over at least some of the adjacent protective layer.
4. A wafer as recited in claim 1 wherein each die further comprises at least one trim pad that is exposed through a trim pad opening formed in the top wafer fabrication passivation layer, and wherein the portions of the patterned copper layer, the first titanium metallization layer and the first aluminum metallization layer that overlie the trim pad form a trim pad stack and the protective layer fully covers the trim pad stack.
5. A wafer as recited in claim 1 further comprising a second titanium metallization layer positioned between the contact pads and the patterned copper layer that acts as an electrically conductive barrier layer between the contact pads and the patterned copper layer, wherein the second titanium metallization layer connects with the first titanium metallization layer to envelop interconnects in the patterned copper layer.
6. The integrated circuit wafer of claim 1 wherein the thickness of the patterned copper layer above the contact pads at least equals the depth of the contact pad openings.
7. The integrated circuit wafer of claim 1 wherein the thickness of the patterned copper layer above the contact pads is at least 50,000 Angstroms.
8. The integrated circuit wafer of claim 1 wherein at least one of the contact openings in the protective layer is positioned laterally offset to the associated contact pad opening in the top wafer fabrication passivation layer.
9. An integrated circuit wafer comprising a multiplicity of dice, the dice each including a multiplicity of integrated circuits and a plurality of contact pads that are exposed through contact pad openings formed in a top wafer fabrication passivation layer, the wafer further including:
a patterned copper layer formed over the top wafer fabrication passivation layer, wherein the patterned copper layer is electrically coupled to at least some of the contact pads through the contact pad openings;
a titanium metallization layer positioned between the contact pads and the patterned copper layer that acts as an electrically conductive barrier layer between the contact pads and the patterned copper layer;
an electrically insulating protective layer that overlies the patterned copper layer and the top wafer fabrication passivation layer, there being a plurality of contact openings in the protective layer; and
a plurality of underbump metallization stacks, each underbump metallization stack being electrically connected to the patterned copper layer through an associated contact opening in the protective layer, wherein peripheral portions of the underbump metallization stacks extend over at least some adjacent portions of the protective layer; and
wherein each die further comprises at least one trim pad that is exposed through a trim pad opening formed in the top wafer fabrication passivation layer, and wherein (i) a segment of the patterned copper layer is electrically coupled to each trim pad, (ii) trim openings are also formed in the protective layer, (iii) a trim pad metallization stack is formed in each trim opening,
the uppermost exposed layer of the trim pad metallization stacks are formed from a non-solder wettable material;
the uppermost exposed layer of the underbump metallization stacks are formed from a solder wettable material; and
the underbump metallization stacks have at least one more layer than the trim pad metallization stacks.
10. The integrated circuit wafer of claim 9 wherein the underbump metallization stack and the trim pad metallization stack include an identical ordered set of metal layers excepting the uppermost exposed layer of the underbump metallization stack.
11. The integrated circuit wafer of claim 9 wherein the underbump metallization stacks and the trim pad metallization stacks each include:
a titanium layer in contact with the patterned copper layer;
an aluminum layer in contact with the titanium layer;
a nickel vanadium layer that overlies the aluminum layer; and
the underbump metallization stacks each include a second copper layer that overlies the nickel vanadium layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A resistive memory device including a memory cell, the memory cell comprising:
a vertical transistor comprising a gate electrode on a surface of a substrate, a gate insulation layer extending along a sidewall of the gate electrode, and a single crystalline silicon layer on the surface of the substrate adjacent to the gate insulation layer, at least a portion of the single crystalline silicon layer defining a channel region that extends in a direction substantially perpendicular to the surface of the substrate; and
a variable resistance layer on the single crystalline silicon layer and electrically insulated from the gate electrode.
2. The resistive memory device of claim 1, wherein the single crystalline silicon layer comprises a plurality of epitaxial layers of alternating conductivity types.
3. The resistive memory device of claim 1, wherein the plurality of epitaxial layers comprise an n-type epitaxial layer, a p-type epitaxial layer, and an n-type epitaxial layer that are sequentially stacked on the substrate, or an n-type epitaxial layer and a p-type epitaxial layer that are sequentially stacked on the substrate.
4. The resistive memory device of claim 1, further comprising a bit line on the variable resistance layer, wherein the variable resistance layer is electrically coupled between the bit line and a sourcedrain region of the vertical transistor in the single crystalline silicon layer.
5. The resistive memory device of claim 4, further comprising:
a device isolation layer including a first portion on the surface of the substrate and extending along a sidewall of the gate electrode opposite the gate insulation layer, and a second portion on the gate electrode and on the gate insulation layer, wherein the first portion extends between the gate electrode and an adjacent resistive memory device on the surface of the substrate, and wherein the second portion extends between the gate electrode and the variable resistance layer.
6. The resistive memory device of claim 4, further comprising:
a device isolation layer on the gate electrode and on the gate insulation layer, wherein the device isolation layer electrically insulates the gate electrode from the bit line.
7. The resistive memory device of claim 6, wherein the device isolation layer further extends onto a portion of the single crystalline silicon layer
8. The resistive memory device of claim 7, wherein the variable resistance layer extends along a portion of the gate insulation layer and is confined below the device isolation layer.
9. The resistive memory device of claim 8, further comprising:
a connection electrode on the variable resistance layer and extending through the device isolation layer to electrically connect the variable resistance layer to the bit line.
10. The resistive memory device of claim 6, wherein the variable resistance layer is on a portion of the single crystalline silicon layer adjacent to the device isolation layer such that the variable resistance layer and the device isolation layer define a substantially planar surface.
11. A resistive memory device, comprising:
a plurality of word lines extending in a first direction on a surface of a substrate and electrically separated from one another by a device isolation layer in a second direction substantially perpendicular to the first direction;
respective gate insulation layers extending along respective sidewalls of the plurality of word lines in the first direction;
a single crystalline silicon layer adjacent to the gate insulation layers and defining at least one channel region that extends in a third direction substantially perpendicular to the surface of the substrate, wherein the word lines, the gate insulation layers, and the single crystalline silicon layer define a vertical transistor array arranged in the first direction and the second direction;
a device isolation layer extending in the first direction on the plurality of word lines and the gate insulation layers;
a variable resistance layer that is electrically insulated from the plurality of word lines by the device isolation layer and is adjacent to the single crystalline silicon layer at a side of the word lines; and
a plurality of bit lines on the variable resistance layer, wherein the plurality of bit lines extend in the second direction substantially perpendicular to the plurality of word lines and are separated from one another in the first direction.
12. The resistive memory device of claim 11, wherein the variable resistance layer is on the single crystalline silicon layer and extends in the first direction substantially parallel to the word lines, and wherein the variable resistance layer electrically couples ones of the plurality of bit lines to respective sourcedrain regions in the single crystalline silicon layer.
13. The resistive memory device of claim 11, wherein the plurality of bit lines are directly on the device isolation layer and the variable resistance layer, or wherein the plurality of bit lines are on a connection electrode on the resistance change layer.
14. The resistive memory device of claim 11, wherein the device isolation layer comprises a first portion on the substrate extending along respective sidewalls of the plurality of word lines opposite the gate insulation layers, and a second portion on the plurality of word lines, the gate insulation layer, and the single crystalline silicon layer.
15. The resistive memory device of claim 11, wherein the device isolation layer extends on the plurality word lines, the gate insulation layers, and portions of the single crystalline silicon layer, and wherein the variable resistance layer extends along portions of the respective gate insulation layers and is confined below the device isolation layer.
16. A resistive memory device, comprising:
a single crystalline silicon layer comprising alternating layers of different conductivity types on a substrate;
a plurality of grooves in the single crystalline silicon layer extending in a first direction, wherein ones of the plurality of grooves are separated from one another in a second direction substantially perpendicular to the first direction,
a respective gate insulation layer and a respective word line in each of the plurality of grooves and extending in the first direction, wherein the word lines, the gate insulation layers, and the single crystalline silicon layer define a vertical transistor array arranged in the first direction and the second direction;
a device isolation layer extending in the first direction on the word lines and the gate insulation layers;
a variable resistance layer on portions of the single crystalline silicon layer outside the plurality of grooves; and
a plurality of bit lines on the resistance change layer and electrically connected thereto, wherein the plurality of bit lines extend in a second direction substantially perpendicular to the word lines and are separated from one another in the first direction.
17. The resistive memory device of claim 16, wherein the device isolation layer comprises a first portion in a trench that is formed in each of the plurality of grooves by etching a portion of the single crystalline silicon layer and a portion of the word line therein, and a second portion that is formed on the word lines and the gate insulation layer in each of the plurality of grooves that are formed by etching a portion of the single crystalline silicon layer.
18. The resistive memory device of claim 16, wherein the device isolation layer is on the word lines, on the gate insulation layer, and on portions of the single crystalline silicon layer.
19. The resistive memory device of claim 16, wherein the device isolation layer is adjacent to the variable resistance layer that is formed on single crystalline silicon layer, and is on the word line and the gate insulation layer such that the variable resistance layer and the device isolation layer define a substantially planar surface.
20. The resistive memory device of claim 16, wherein the variable resistance layer extends in the first direction on the single crystalline silicon layer at sides of the word lines and the gate insulation layers, and wherein the variable resistance layer electrically couples ones of the plurality of bit lines to respective sourcedrain regions in the single crystalline silicon layer.