1. A method for adjusting a compliance voltage in a stimulator device, comprising:
using at least one source circuit and at least one sink circuit to provide stimulation pulses to a load between at least two electrodes;
during the stimulation pulses, measuring at least one first voltage across the at least one source circuit and measuring at least one second voltage across the at least one sink circuit; and
using the measured first and second voltages to adjust the compliance voltage, wherein the compliance voltage is formed across the series connection of the at least one source circuit, the load, and the at least one sink circuit.
2. The method of claim 1, wherein the at least one first voltage and the at least one second voltage are not measured simultaneously.
3. The method of claim 1, wherein only the at least one first voltage is measured during a first of the stimulation pulses, and wherein only the at least one second voltage is measured during a second of the stimulation pulses.
4. The method of claim 1, wherein the first and second voltages are used to adjust the compliance voltage by comparing the first and second voltages to at least one threshold.
5. The method of claim 4, wherein there is a first threshold and a second threshold, and wherein the at least one first voltage is compared to the first threshold, and wherein the at least one second voltage is compared to the second threshold.
6. The method of claim 4, wherein the compliance voltage is adjusted to a lower value if either of the first or second voltages is higher than the at least one threshold.
7. The method of claim 6, wherein the at least one threshold is indicative of saturation of output transistors across which the first and second voltages are measured.
8. The method of claim 1, further comprising generating the compliance voltage from a battery within the stimulator device.
9. The method of claim 1, wherein using the first and second voltages to adjust the compliance voltage comprises:
assessing the first and second voltages to determine whether they are within at least one guard band range of voltages; and
adjusting the compliance voltage to bring the first and second voltages within the at least one guard band range of voltages.
10. The method of claim 9, wherein there is a first guard band range of voltages and a second guard band range of voltages, and wherein the at least one first voltage is assessed to determine whether they are within the first guardband range of voltages, and wherein the at least one second voltage is assessed to determine whether they are within the second guardband range of voltages.
11. The method of claim 9, wherein the compliance voltage is adjusted to a lower value if either of first or second voltages is higher than the at least one guard band range of voltages.
12. The method of claim 9, wherein the at least one guard band range of voltages is set in recognition of the saturation threshold of output transistors across which the first and second voltages are measured in the at least one source circuit and the at least one sink circuit.
13. The method of claim 1, further comprising, during interphase periods in which the stimulation pulses are not provided, measuring at least one third voltage across the at least one source circuit and measuring at least one fourth voltage across the at least one sink circuit.
14. The method of claim 13, further comprising using the using the first, second, third, and fourth voltages to adjust the compliance voltage.
15. A method for adjusting a compliance voltage in a stimulator device, comprising:
using at least one source circuit and at least one sink circuit to provide a first stimulation pulse to a load between at least two electrodes;
during the first stimulation pulse, measuring at least one first voltage across the at least one source circuit;
using the at least one source circuit and the at least one sink circuit to provide a second stimulation pulse to the load;
during the second stimulation pulse, measuring at least one second voltage across the at least one sink circuit; and
using the at least one first voltage and the at least one second voltage to adjust the compliance voltage,
wherein the compliance voltage is formed across the series connection of the at least one source circuit, the load, and the at least one sink circuit.
16. The method of claim 15, wherein the at least one first voltage and the at least one second voltage are used to adjust the compliance voltage by comparing them to at least one threshold.
17. The method of claim 16, wherein there is a first threshold and a second threshold, and wherein the at least one first voltage is compared to the first threshold, and wherein the at least one second voltage is compared to the second threshold.
18. The method of claim 15, further comprising generating the compliance voltage from a battery within the stimulator device.
19. The method of claim 15, wherein using the at least one first voltage and the at least one second voltage to adjust the compliance voltage comprises:
assessing the at least one first voltage to determine whether they are within a first guard band range of voltages;
assessing the at least one second voltage to determine whether they are within a second guard band range of voltages; and
adjusting the compliance voltage to bring the at least one first voltage within the first guardband range of voltages and to bring the at least one second voltage within the second guardband range of voltages.
20. The method of claim 15, further comprising, during interphase periods in which neither the first or second stimulation pulses are provided, measuring at least one third voltage across the at least one source circuit and measuring at least one fourth voltage across the at least one sink circuit.
21. The method of claim 20, further comprising using the first, second, third and fourth voltages to adjust the compliance voltage.
22. An implantable medical device, comprising:
a source circuit coupled to a compliance voltage, wherein the source circuit is configured to provide a current to at least a first electrode;
a sink circuit coupled to a reference voltage, wherein the sink circuit is configured to sink the current from at least a second electrode;
voltage sensor circuitry configured to measure a first voltage across the source circuit and for measuring a second voltage across the sink circuit; and
regulator circuitry configured to adjust the compliance voltage in accordance with the first and second voltages.
23. The implantable medical device of claim 22, further comprising a switching matrix, wherein the switching matrix is configured to selectively couple the first and second voltages to the voltage sensor circuitry.
24. The implantable medical device of claim 22, further comprising a first switching matrix for coupling the source circuit to the first electrode, and a second switching matrix for coupling the sink circuit to the second electrode.
25. The implantable medical device of claim 22, further comprising a first switch for coupling the source circuit to the first electrode, and a second switch for coupling the sink circuit to the second electrode.
26. The implantable medical device of claim 25, wherein the first voltage comprises a voltage across the source circuit and the first switch, and wherein the second voltage comprises a voltage across the sink circuit and the second switch.
27. The implantable medical device of claim 25, wherein the first voltage comprises a voltage across the source circuit but not across the first switch, and wherein the second voltage comprises a voltage across the sink circuit but not across the second switch.
28. The implantable medical device of claim 22, wherein the source and sink circuits comprise current mirrors.
29. The stimulator device of claim 22, wherein the first voltage includes a voltage drop across a first output transistor in the source circuit, and wherein the second voltage includes a voltage drop across a second output transistor in the sink circuit.
30. The simulator device of claim 29, wherein the regulator circuitry is configured to adjust the compliance voltage to change the first voltage such that the first output transistor is in saturation, and to change the second voltage such that the second output transistor is in saturation.
31. The simulator device of claim 22, wherein the regulator circuitry is configured to adjust the compliance voltage to reduce the first voltage below a first threshold, and to reduce the second voltage below a second threshold.
32. The stimulator device of claim 17, further comprising a battery, wherein the regulator circuit derives the compliance voltage from the battery.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor apparatus comprising:
first and second bus-interface circuits;
a first memory core connected to the first bus-interface circuit through a first data bus, the first memory core being connected to a first access control signal output from the first bus-interface circuit;
a second memory core connected to the second bus-interface circuit through a second data bus; and
a select circuit that selectively connects one of the first access control signal and a second access control signal output from the second bus-interface circuit to the second memory core.
2. The semiconductor apparatus according to claim 1, wherein the select circuit selects an access control signal to be connected to the second memory core according to an externally-supplied switching signal.
3. The semiconductor apparatus according to claim 1, further comprising:
a third bus-interface circuit; and
a third memory core connected to the third bus-interface circuit through a third data bus, wherein
the select circuit selectively connects one of the first access control signal and a third access control signal output from the third bus-interface circuit to the third memory core.
4. The semiconductor apparatus according to claim 3, wherein the select circuit selects an access control signal to be connected to the third memory core according to an externally-supplied switching signal.
5. A network apparatus comprising a semiconductor apparatus according to claim 1.
6. A semiconductor apparatus comprising:
a plurality of memory cores;
a plurality of interface circuits including a first interface circuit, a data signal path being set between each of the plurality of interface circuits and a different one of storage areas of the plurality of memory cores; and
a path switching circuit that sets, according to a switching signal, whether the first interface circuit supplies an access control signal to one memory core or to more than one memory core.
7. The semiconductor apparatus according to claim 6, wherein the switching signal is determined according to a data width of a data signal exchanged between the semiconductor apparatus and an external circuit that supplies the access control signal to the first interface circuit.
8. The semiconductor apparatus according to claim 6, wherein the path switching circuit sets a path of the data signal between the plurality of interface circuits and the plurality of memory cores so as to permit each of the plurality of interface circuits to interface an exchange of the data signal for a different one of the plurality of memory cores.
9. The semiconductor apparatus according to claim 6, wherein the path switching circuit sets a path of the data signal between the plurality of interface circuits and the memory cores so as to permit each of the plurality of interface circuits to interface an exchange of the data signal for a different one of storage areas of one of the plurality of memory cores.
10. The semiconductor apparatus according to claim 6, wherein the external circuit is formed on a field programmable gate array whose circuit configuration is rewritable.
11. The semiconductor apparatus according to claim 6, wherein an input terminal of an interface circuit that does not interface an exchange of the data signal among the plurality of interface circuits is fixed at a predetermined logic level.
12. A network apparatus comprising a semiconductor apparatus according to claim 6.
13. The semiconductor apparatus according to claim 1, wherein, in response to the select circuit selectively connecting the first access control signal to the second memory core, the first memory core and the second memory core each receive the first access control signal.
14. A semiconductor apparatus comprising:
a first memory core configured to receive a first data signal and a first access control signal; and
a second memory core configured to receive a second data signal and a selected access control signal, wherein
in response to a selection signal supplied to the semiconductor apparatus having a first value, the selected access control signal is the first access control signal, and in response to the selection signal having a second value, the selected access control signal is a second control signal.
15. The semiconductor apparatus according to claim 14, further comprising:
a path selection circuit configured to receive the first access control signal, the second access control signal, and the selection signal, and to output the selected access control signal.
16. The semiconductor apparatus according to claim 15, further comprising:
a first interface circuit configured to output the first access control signal; and
a second interface circuit configured to output the second access control signal.
17. The semiconductor apparatus according to claim 16, further comprising:
a first path configured to transmit the first access control signal from the first interface circuit to the first memory core and to the path selection circuit;
a second path configured to transmit the second access control signal from the second interface circuit to the path control circuit; and
a third path configured to transmit the selected access control signal from the path control circuit to the second memory core.