1. A method of fabricating a semiconductor device, the method comprising:
(a) forming on a substrate an interconnect stack layer that includes a plurality of layers with interconnecting metal overlying the substrate;
(b) subsequent to step (a), forming a crack stop trench in the interconnect stack layer; and
(c) filling the crack stop trench with a prescribed material.
2. The method of claim 1 wherein the crack stop trench is continuous and surrounds the interconnect stack layer.
3. The method of claim 1 wherein the prescribed material is a carbon polymer dielectric.
4. The method of claim 1 wherein the step of forming the interconnect stack layer comprises:
(d) forming on the substrate a dielectric layer that includes an organosilicon material;
(e) forming a via photoresist pattern over the dielectric layer;
(f) etching an interconnect via in the dielectric layer using the via photoresist pattern as an etch mask;
(g) removing the via photoresist pattern;
(h) forming a trench photoresist pattern over the dielectric layer;
(i) etching an interconnect trench in the dielectric layer using the trench photoresist pattern as an etch mask, said trench being connected to the interconnect via;
(j) removing the trench photoresist pattern;
(k) forming a barrier layer overlying the interconnect via and the interconnect trench;
(l) completing interconnections by filling the interconnect trench and the interconnect via with copper.
5. The method of claim 1 wherein said crack stop trench has a lateral dimension greater than a lateral dimension of a trench in said interconnect stack layer.
6. The method of claim 1 wherein said crack stop trench has a lateral dimension one or more orders of magnitude greater than a lateral dimension of a trench in said interconnect stack layer.
7. The method of claim 1 wherein the barrier layer is selected from the group consisting of tantalum, tantalum nitride, titanium, titanium silicide or zircuonium.
8. The method of claim 1, further comprising, before step (d): forming a lower interconnection on the substrate; and forming an etch stop layer on the lower interconnection.
9. The method of claim 8, wherein the etch stop layer is formed of at least one of SiC, SiN, and SiCN.
10. The method of claim 4, wherein the dielectric layer is formed using chemical vapor deposition.
11. The method of claim 4, further comprising, before step (e), forming a capping layer on the dielectric layer, wherein in step (f), the interconnect via is formed in the capping layer and the dielectric layer.
12. The method of claim 11, wherein the capping layer is formed of at least one of SiO2, SiOF, SiON, SiC, SiN and SiCN.
13. The method of claim 11, wherein step (e) comprises: forming a photoresist pattern on the capping layer to define the via; and etching the capping layer and the dielectric layer using the photoresist pattern as an etch mask.
14. The method of claim 13 wherein the trench photoresist pattern in formed on the capping layer.
15. The method of claim 13, wherein the etching is a dry etch using CxFy or CxHyFz as a main etching gas, and removing the photoresist pattern uses an H2-based plasma.
16. A semiconductor wafer comprising:
a substrate;
an interconnect stack layer that includes a plurality of layers with interconnecting metal overlying the substrate;
at least one crack stop trench located in the interconnect stack layer, said crack stop trench being filled with a prescribed material different from the interconnecting metal.
17. The semiconductor wafer of claim 16 wherein each of the crack stop trenches are continuous and extend around a periphery of one of the dies areas.
18. The semiconductor wafer of claim 16 wherein the prescribed material is a carbon polymer dielectric.
19. The semiconductor wafer of claim 16 wherein said crack stop trench has a lateral dimension greater than a lateral dimension of a trench in said interconnect stack layer.
20. The semiconductor wafer of claim 16 wherein said crack stop trench has a lateral dimension one or more orders of magnitude greater than a lateral dimension of a trench in said interconnect stack layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method comprising:
performing a plurality of communications over a plurality of signal lines coupled between a transmitter and a receiver according to different parameters;
determining, for each of the plurality of signal lines, whether a correct data value is received by the receiver for each of the plurality of communications;
storing data transmission results according to each of the parameters for which transmissions are conducted in a storage mechanism, wherein the data transmission results are indicative of whether correct data values were received for the plurality of communications, and wherein the storage mechanism includes, for each of the plurality of signal lines, a table having a plurality of rows each corresponding to a first one of the different parameters and a plurality of columns each corresponding to a second one of the different parameters; and
selecting designated parameters from the table corresponding to each of the plurality of signal lines for subsequent communications between the transmitter and the receiver, wherein the first one of the different parameters is a different sampling voltage threshold level.
2. The method as recited in claim 1 further comprising the receiver indicating to the transmitter a voltage level for subsequent communications.
3. The method as recited in claim 1 further comprising the receiver setting voltage threshold levels, wherein setting the voltage threshold levels determine a voltage threshold level for which the receiver will recognize a logic high and a voltage threshold level for which the receiver will recognize a logic low.
4. The method as recited in claim 1, wherein the transmitter is a source synchronous transmitter and the receiver is a source synchronous receiver.
5. The method as recited in claim 4, wherein the source synchronous transmitter includes a adjustable voltage source, wherein the adjustable voltage source is configured to generate a voltage level at which signals are to be transmitted over one or more of the plurality of signal lines.
6. The method as recited in claim 1, wherein the communications are conducted in conjunction. with a built-in self-test (BIST).
7. A system comprising:
A transmitter; and
a receiver coupled to the transmitter by a plurality of signal lines;
wherein the transmitter is configured to conduct a plurality of data transmissions over the plurality of signal lines;
wherein the receiver is configured to:
receive the data transmissions and to sample data into the receiver according to different parameters;
determine whether a correct data value is received by the receiver for each data transmission;
wherein the system further includes a storage mechanism, wherein the storage mechanism includes, for each of the plurality of signal lines, a table having a plurality of rows each corresponding to a first one of the different parameters and a plurality of columns each corresponding to a second one of the different parameters;
and wherein the system is further configured to:
store data transmission results in the storage mechanism, wherein the data transmission results are indicative of whether correct data values were received for the data transmissions; and
select designated parameters from the table corresponding to each of the plurality of signal lines for subsequent data transmissions, wherein the first one of the different parameters is a different sampling voltage threshold level.
8. The system as recited in claim 7, wherein the receiver is configured to provide an indication to the transmitter of a voltage level for subsequent data transmissions.
9. The system as recited in claim 7, wherein the receiver is configured to adjust voltage threshold levels, wherein the voltage threshold levels determine a voltage level at which the receiver will recognize a logic high and a voltage level at which the receiver will recognize a logic low.
10. The system as recited in claim 7, wherein the transmitter is a source synchronous transmitter and the receiver is a source synchronous receiver.
11. The system as recited in claim 10, wherein the source synchronous transmitter includes a adjustable voltage source, wherein the adjustable voltage source is configured to generate a voltage level at which signals are to be transmitted over one or more of the plurality of signal lines.
12. The system as recited in claim 7, wherein the transmitter and the receiver are configured to perform a built-in self-test (BIST, wherein the data transmissions are conducted in conjunction with the BIST.
13. An integrated circuit comprising:
a receiver port, the receiver port coupled to a plurality of signal lines, wherein the receiver port is configured to receive data transmissions over the plurality of signal lines from a transmitter port, wherein the data transmissions include one or more test vectors;
a storage mechanism, the storage mechanism configured to store results obtained from the reception of test vectors transmitted by the transmitter port, wherein the results are indicative of whether a correct data value was received for test vector, wherein the storage mechanism includes, for each of the plurality of signal lines, a table having a plurality of rows each corresponding to a first parameter and a plurality of columns each corresponding to a second parameter; and
a control unit coupled to the receiver and the storage mechanism, wherein the control unit is configured to select parameters for each of the plurality of signal lines from the corresponding table in the storage mechanism for subsequent data transmissions from the transmitter, wherein the first parameter is a sampling voltage threshold level.
14. The integrated circuit as recited in claim 13, wherein the receiver is configured to adjust voltage threshold levels, wherein the voltage threshold levels determine a voltage level at which the receiver will recognize a logic high and a voltage level at which the receiver will recognize a logic low.
15. The integrated circuit as recited in claim 13, wherein the receiver is configured to provide an indication to a transmitter of a voltage level for subsequent data transmissions.
16. The integrated circuit as recited in claim 15, wherein the transmitter is a source synchronous transmitter and the receiver is a source synchronous receiver.
17. The integrated circuit as recited in claim 15, wherein the integrated circuit comprises the transmitter.
18. The integrated circuit as recited in claim 17, wherein the source synchronous transmitter includes a adjustable voltage source, wherein the adjustable voltage source is configured to generate a voltage level at which signals are to be transmitted over one or more of the plurality of signal lines.
19. The integrated circuit as recited in claim 13, wherein the receiver port is configured to receive the data transmissions in conjunction with a built-in self-test (BIST).
20. The integrated circuit as recited in claim 13, wherein the parameters determine a point within an eye pattern at which a signal is sampled.