1. A method for selective image distribution using a processor, comprising:
determining whether an image comprises a non-display image layer and a display image layer; and
generating, using the processor, a share image by synthesizing the display image layer.
2. The method of claim 1, wherein the image comprises at least one of a graphic image, a moving picture, a text, data, and a control mechanism.
3. The method of claim 1, further comprising transmitting the share image to a device, wherein the transmitting the share image comprises:
storing the share image in a sharing buffer generating unit;
capturing an instance of the share image; and
encoding the instance of the share image for transmission.
4. The method of claim 1, further comprising:
generating a main image by synthesizing the display image layer and the non-display image layer.
5. The method of claim 1, wherein an image layer of the image is determined to be the non-display image layer if the image layer is determined to comprise a non-display item.
6. The method of claim 1, wherein an image layer of the image is determined to be the non-display image layer based on a registered table.
7. The method of claim 1, wherein an image layer of the image is determined to be the non-display image layer according to a reference condition.
8. The method of claim 1, further comprising receiving an input for designating an image layer of the image as the non-display image layer.
9. The method of claim 1, wherein the share image comprises only the display image layer among the display image layer and the non-display image layer.
10. A device, comprising:
a layer configuring unit to determine whether an image comprises a non-display image layer and a display image layer; and
a layer synthesizing unit to synthesize the display image layer to generate a share image.
11. The device of claim 10, wherein the image comprises at least one of a graphic image, a moving picture, a text, data, and a control mechanism.
12. The device of claim 10, further comprising:
a communication unit to transmit the share image to another device;
a sharing buffer generating unit to store the share image;
a capture unit to capture an instance of the share image; and
an encoding unit to encode the instance of the share image.
13. The device of claim 10, wherein the layer synthesizing unit generates a main image by synthesizing the display image layer and the non-display image layer.
14. The device of claim 10, wherein an image layer of the image is determined to be the non-display image layer if the image layer is determined to comprise a non-display item.
15. The device of claim 10, wherein an image layer of the image is determined to be the non-display image layer based on a registered table.
16. The device of claim 10, wherein an image layer of the image is determined to be the non-display image layer according to a reference condition.
17. The device of claim 10, wherein the layer configuring unit receives an input to designate an image layer of the image as the non-display image layer.
18. The device of claim 10, wherein the share image comprises only the display image layer among the display image layer and the non-display image layer.
19. The device of claim 10, further comprising:
a share buffer generating unit to store the share image; and
a main buffer generating unit to store the main image.
20. A method for selective image distribution using a processor, comprising:
loading an image provided by a source device as a plurality of image layers;
determining whether the plurality of image layers comprise a non-display item;
registering the image layer comprising the non-display item as a non-display image layer;
synthesizing, using the processor, non-registered image layers for generating a share image; and
transmitting the share image to a sink device.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for a phase change memory programming, providing:
a pulse that has at least one leading portion with essentially non-zero duration,
followed by an intermediate portion, and then
followed by at least one trailing portion
in order to transform phase-change alloy into low-resistance mostly crystalline set state.
2. The method of claim 1 wherein duration of the leading portion of the set pulse is between 5 ns and 1 us.
3. The method of claim 1 wherein the set pulse amplitude does not melt phase change alloy.
4. The method of claim 1 wherein the leading portion of the set pulse has 2 or more segments.
5. The method of claim 1 wherein the leading portion of the set pulse has 3 segments.
6. The method of claim 4 wherein duration of the leading portion segment is between 5 ns and 1 us.
7. The method of claim 1 wherein duration of the trailing portion of the set pulse is between 0 and 1 us.
8. The method of claim 1 wherein the trailing portion of the set pulse has 2 or more segments.
9. The method of claim 8 wherein duration of the trailing portion segment is shorter than 1 us.
10. The method of claim 1 wherein duration of the intermediate portion of the set pulse is shorter than 1 us.
11. The method of claim 1 wherein a change of amplitude during the intermediate portion of the set pulse is below 20% of the amplitude of this portion.
12. The method of claim 1 wherein amplitude of the set pulse is between 1 uA and 2 mA.
13. The method of claim 1 wherein a threshold switching occurs during the leading portion or one of its segments.
14. The method of claim 1 wherein a nucleation occurs during the leading portion or one of its segments.
15. The method of claim 1 wherein a crystallization occurs mostly during the leading portion or one of its segments.
16. The method of claim 1 wherein a crystal growth and coalescence of crystals occurs mostly during the intermediate portion of the set pulse.
17. The method of claim 1 wherein a stabilization of morphology of nano-crystals occurs mostly during the trailing portion or one of its segments.
18. A method for a phase change memory programming, providing:
a pulse that has at least one leading portion with essentially non-zero duration,
followed by an intermediate portion, and then
followed by at least one trailing portion
in order to transform phase-change alloy into high-resistance mostly amorphous reset state.
19. The method of claim 18 wherein duration of the leading portion of the reset pulse is between 0.1 ns and 100 ns.
20. The method of claim 18 wherein the reset pulse amplitude melts phase change alloy.
21. The method of claim 18 wherein the leading portion of the reset pulse has 2 or more segments.
22. The method of claim 21 wherein duration of the leading portion segment is between 0.1 ns or 100 ns.
23. The method of claim 18 wherein duration of the trailing portion of the reset pulse is between 0 and 50 ns.
24. The method of claim 18 wherein the trailing portion of the reset pulse has 2 or more segments.
25. The method of claim 18 wherein the trailing portion of the reset pulse has 3 segments.
26. The method of claim 24 wherein duration of the trailing portion segment is shorter than 50 ns.
27. The method of claim 18 wherein duration of the intermediate portion of the reset pulse is shorter than 50 ns.
28. The method of claim 18 wherein a change of amplitude during the intermediate portion of the reset pulse is below 20% of the amplitude of this portion.
29. The method of claim 18 wherein amplitude of the reset pulse is between 10 uA and 3 mA.
30. The method of claim 18 wherein a temperature within phase change alloy reaches the melting point of this alloy during the leading portion or one of its segment.
31. The method of claim 18 wherein a melt fusion occurs mostly during the leading portion or one of its segments.
32. The method of claim 18 wherein a mixing and a homogenization of the melt occurs mostly during the intermediate portion of the reset pulse.
33. The method of claim 18 wherein quenching of phase change alloy into mostly amorphous phase occurs mostly during the trailing portion or one of its segments.
34. The method of claim 18 wherein annealing of amorphous phase change alloy occurs mostly during the trailing portion or one of its segments.
35. The method of claim 4 wherein rates of the amplitude change are different during various segment of the leading portion of the set pulse.
36. The method of claim 8 wherein rates of the amplitude change are different during various segment of the trailing portion of the set pulse.
37. The method of claim 21 wherein rates of the amplitude change are different during various segment of the leading portion of the reset pulse.
38. The method of claim 24 wherein rates of the amplitude change are different during various segment of the trailing portion of the reset pulse.
39. The method of claim 4 wherein rate of the amplitude change during the first segment of the leading portion of the set pulse is between 1E5Vsec and 1E10Vsec.
40. The method of claim 4 wherein rate of the amplitude change during the first segment of the leading portion of the set pulse is between 1 mAsec and 1E8Asec.
41. The method of claim 4 wherein rate of the amplitude change during the second segment of the leading portion of the set pulse is below 1E6Asec.
42. The method of claim 4 wherein rate of the amplitude change during the third segment of the leading portion of the set pulse is below 5E6Asec.
43. The method of claim 8 wherein rate of the amplitude change during the first segment of the trailing portion of the set pulse is between 20 Asec and 2E7Asec.
44. The method of claim 8 wherein rate of the amplitude change during the second segment of the trailing portion of the set pulse is between 2E2Asec and 1E8Asec.
45. The method of claim 21 wherein rate of the amplitude change during the first segment of the leading portion of the reset pulse is between 1E3Asec and 1E9Asec.
46. The method of claim 21 wherein rate of the amplitude change during the second segment of the leading portion of the reset pulse is below 1E6Asec.
47. The method of claim 24 wherein rate of the amplitude change during the first segment of the trailing portion of the reset pulse is above 1E7Asec.
48. The method of claim 24 wherein rate of the amplitude change during the second segment of the trailing portion of the reset pulse is below 1E5Asec.
49. The method of claim 24 wherein rate of the amplitude change during the third segment of the trailing portion of the reset pulse is between 1E3Asec and 1E10Asec.
50. An apparatus comprising:
a phase change memory; and
a write circuit coupled with the phase change memory; and
other interface devices coupled with the phase change memory and the write circuit.