1. A semiconductor structure comprising:
a substrate formed of a first conductivity type;
an epitaxial layer formed over the substrate;
a first well region of a second conductivity type formed in the epitaxial layer;
a second well region of the second conductivity type formed in the epitaxial layer and spaced apart from the first well region;
a third well region of the first conductivity type formed between the first well region and the second well region;
a field region of the first conductivity type formed in a surface of the third well region and spaced apart from the first well region and the second well region; and
a drain region of the first conductivity type formed in a surface of and extending into the field region.
2. The semiconductor structure as set forth in claim 1, wherein:
the first conductivity type is P-type; and
the second conductivity type is N-type.
3. The semiconductor structure as set forth in claim 1, wherein:
the first conductivity type is N-type; and
the second conductivity type is P-type.
4. The semiconductor structure as set forth in claim 1, further comprising a buried region of the second conductivity type formed in the epitaxial layer and extending into the substrate, wherein:
the first well region extends from a surface of the epitaxial layer to an upper extent of the buried region, the first well region overlying a portion of the buried region and extending laterally beyond the buried region;
the second well region extends from the surface of the epitaxial layer to the upper extent of the buried region, the second well region overlying a portion of the buried region and extending laterally beyond the buried region; and
the field region is spaced apart from the buried region.
5. The semiconductor structure as set forth in claim 4, further comprising:
a first insulation region overlying a portion of the second well region, a portion of the third well, and a portion of the field region; and
a gate electrode formed on the first insulation region above the portion of the second well region and extending over a portion of the third well region.
6. The semiconductor structure as set forth in claim 5, further comprising a source region formed in a surface of and extending into the second well region.
7. The semiconductor structure as set forth in claim 6, wherein the source region comprises:
a first portion of the second conductivity type; and
a second portion of the first conductivity type, the second portion abutting the first portion.
8. The semiconductor structure as set forth in claim 5, further comprising:
a second insulation region overlying and extending into the first well region, a portion of the third well region, and a portion of the field region, the second insulation region extending to the drain region;
a fourth well region of the first conductivity type adjacent to the second well region opposite the third well region; and
a third insulation region overlying and extending into the fourth well region and a portion of the second well region, the third insulation region also extending to the source region.
9. The semiconductor structure as set forth in claim 8, wherein the insulation regions comprise field oxide.
10. A method, comprising:
forming a buried layer in a first-conductivity type substrate;
depositing an epitaxial layer of the first conductivity type over the substrate and the buried layer;
forming first and second wells of a second conductivity type in the epitaxial layer;
forming a third well of the first conductivity type between the first and second wells;
forming a field region of the first conductivity type in the third well, the field region being spaced apart from the first and second wells and the buried layer; and
forming a drain region of the first conductivity type in the field region.
11. The method as set forth in claim 10, wherein:
the first conductivity type is P-type;
the second conductivity type is N-type; and
the forming of a field region is preceded by driving in the first, second, and third wells.
12. The method as set forth in claim 10, wherein:
the first conductivity type is N-type;
the second conductivity type is P-type; and
the forming of a field region is preceded by driving in the first, second, and third wells.
13. The method as set forth in claim 10, wherein:
the buried layer is formed of material having the second conductivity type;
the forming of the first and second wells comprises implanting atoms of the second conductivity type into a surface of the epitaxial layer; and
the forming of the third well comprises implanting atoms of the first conductivity type into the surface of the epitaxial layer.
14. The method as set forth in claim 13, wherein the forming of the first, second, and third wells further comprises driving the wells to a depth about the same as that of an upper extent of the buried layer.
15. The method as set forth in claim 10, further comprising:
forming a first insulation layer overlying a portion of the second well, a portion of the third well, and a portion of the field region; and
forming a second insulation layer overlying a portion of the first well, a portion of the third well, and a portion of the field region, the first insulation layer being separated from the second insulation layer.
16. The method as set forth in claim 15, wherein the forming of the first and second insulation layers comprises:
depositing an oxide layer; and
patterning and etching the oxide layer.
17. The method as set forth in claim 15, wherein the forming of the first and second insulation layers comprises local oxidation of silicon.
18. The method as set forth in claim 10, further comprising:
forming a lightly doped drain region of the first conductivity type in the field region in a space between the first and second insulation regions; and
forming a source region in a surface of the second well.
19. The method as set forth in claim 15, wherein the forming of the source region comprises:
forming a first region having the second conductivity type; and
forming a second region having the first conductivity type.
20. A semiconductor structure fabricated according to the method set forth in claim 10.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A bi-directional power converter, which operates as a step down converter in a first direction and a step up converter in a second direction, comprising:
one reactive element for storing energy when operating in the first direction and the second direction;
a plurality of switching elements for selectively coupling the one reactive element to one of two or more power sources; and
mode selection circuitry for selectively coupling the bi-directional power converter to a first power source when operating as a step down converter and to a second power source when operating a step up converter, such that when the bi-directional power converter is operating as the step up converter in the second direction, the bi-directional power converter is configured to deliver power to a load at the first power source through a power component of a communications link; the first power source being configured for supplying power to the power converter when the power converter is operating as the step down converter, and the second power source being configured for supplying power to the power converter when the power converter is operating as the step up converter,
the power converter being configured for providing power from the reactive element to a battery and to an electronic device when the power converter is operating as the step down converter.
2. The bi-directional power converter of claim 1 configured to provide power to a mobile device via a USB link when operating as a step up converter.
3. The bi-directional power converter of claim 1 further comprising a battery charging circuit.
4. The bi-directional power converter of claim 3 wherein the battery charging circuit is used to regulate power provided to an energy storage device when the bi-directional power converter operating as a step down converter.
5. The bi-directional power converter of claim 1 further comprising control circuitry coupled to the mode selection circuitry, the control circuitry controlling the plurality of switches such that the bi-directional power converter operates in either the step up or step down mode in response to a mode selection signal provided by the mode selection circuitry.
6. The bi-directional power converter of claim 5 wherein the control circuitry controls the duty cycle of at least one of the plurality of switches such that the bi-directional power converter provides a desired regulated output voltage.
7. The bi-directional power converter of claim 1 wherein the mode selection circuitry further comprises sensing circuitry.
8. The bi-directional power converter of claim 7 wherein the sensing circuitry includes a comparison circuit.
9. The bi-directional power converter of claim 1 wherein the first power source is a power adapter.
10. The bi-directional power converter of claim 1 wherein the second power source is a battery of a mobile device.
11. The bi-directional power converter of claim 1 wherein voltage provided by the battery is used for powering the electronic device.
12. A bi-directional DC to DC power converter, which operates as a buck converter in a first direction and a boost converter in a second direction, comprising:
one reactive element for storing energy when operating in either the first direction or the second direction;
a plurality of switching elements for selectively coupling the one reactive element to one of two or more power sources; and
control circuitry controlling the plurality of switches such that the bi-directional power converter operates in either a buck mode or boost mode, such that when the bi-directional power converter is operating as the boost converter in the second direction, the bi-directional power converter is configured to deliver power to a load at a first power source through a power component of a communications link; the first power source being configured for supplying power to the power converter when the power converter is operating as the buck converter,
the power converter being configured for providing power from the reactive element to a battery and to an electronic device when the power converter is operating as the buck converter.
13. The bi-directional power converter of claim 12 configured to provide power to a mobile device via a USB link when operating as a boost converter.
14. The bi-directional power converter of claim 12 configured to provide power sufficient to operate a mobile device when operating as a buck converter.
15. The bi-directional power converter of claim 12 further comprising a battery charging circuit.
16. The bi-directional power converter of claim 15 wherein the battery charging circuit is used to regulate power provided to an energy storage device when the bi-directional power converter operating as a buck converter.
17. The bi-directional power converter of claim 1 further comprising mode selection circuitry coupled to the control circuitry for selectively coupling the bi-directional power converter to the first power source when operating as the buck converter and to a second power source when operating as the boost converter.
18. The bi-directional power converter of claim 17 wherein the control circuitry controls the duty cycle of at least one of the plurality of switches such that the bi-directional power converter provides a desired regulated output voltage.
19. The bi-directional power converter of claim 17 wherein the mode selection circuitry further comprises sensing circuitry.
20. The bi-directional power converter of claim 19 wherein the sensing circuitry includes a comparison circuit.
21. The bi-directional power converter of claim 12 wherein the second power source is a battery of a mobile device.
22. The bi-directional power converter of claim 12 wherein the control circuitry is configured to determine whether to operate the converter in the buck mode or in the boost mode based on a type of connector coupled to the power converter.