1. A memory system comprising:
a memory module which comprises a plurality of nonvolatile memory cells with a plurality of pages and line-and-space word lines to which more than one of the memory cells are connected; and
a controller which receives write data from a host device,
creates a first error correction code for each page based on the write data stored on a same page connected to a same word line,
creates a second error correction code in units of one or more of the memory cells based on the write data stored in the memory cells,
adds the first and second error correction codes to the write data,
stores the first-and-second-error-correction-codes-added data on the pages in the memory module,
makes a first error correction of the first-and-second-error-correction-codes-added data by using the first error correction code, and
identifies the memory cell that has made an error by using the second error correction code for the first-and-second-error-correction-codes-added data when the first error correction has failed.
2. The memory system of claim 1, wherein the controller decreases the reliability level of data stored in the memory cell that has made a hard error and makes an error correction of the data using the first error correction code.
3. The memory system of claim 1, wherein the controller comprises a table where an area is specified for each threshold distribution of data in the memory cells and creates the second error correction code for each of the memory cells based on the write data stored in the memory cells and the table.
4. The memory system of claim 3, wherein the table is such that a code of an odd-numbered area in ascending order of threshold voltage differs from a code of an even-numbered area, and
the controller creates the second error correction code for each of the memory cells based on the write data stored in the memory cells and the code.
5. The memory system of claim 1, wherein the page comprises
a first area which stores write data provided by the host device,
a second area which stores a first error correction code, a low-density parity code, encoded based on data stored on the same page connected to the same word line in the first area, and
a third area which stores a second error correction code, a BCH code, encoded based on multilevel data stored in the same memory cell in the first area.
6. The memory system of claim 1, wherein the controller performs hard bit decision and soft bit decision on the first-and-second-error-correction-codes-added data supplied from the memory module, soft bit decision making a more detailed threshold decision than hard bit decision, and
uses the soft bit decision result when making the second error correction.
7. A memory system comprising:
a plurality of nonvolatile memory cells with a plurality of pages;
a memory module which comprises a plurality of nonvolatile memory cells with a plurality of pages and line-and-space word lines to which more than one of the memory cells are connected; and
a controller which receives write data from a host device,
creates an error correction code in units of one or more of the memory cells based on the write data stored in the memory cells,
adds the error correction code to the write data,
stores the error-correction-code-added write data in the memory module, and
makes an error correction of the error-correction-code-added data supplied from the memory module by using the error correction code.
8. The memory system of claim 7, wherein the controller comprises a table where an area is specified for each threshold distribution of data in the memory cells and creates the error correction code for each of the memory cells based on the write data stored in the memory cells and the table.
9. The memory system of claim 8, wherein the table is such that numbers are allocated to the areas in ascending order of threshold voltage and codes of the areas correspond to the numbers of the areas, and
the controller creates the error correction code for each of the memory cells based on the write data stored in the memory cells and the codes.
10. The memory system of claim 7, wherein the controller comprises a table where a plurality of areas are specified for each threshold distribution of data in the memory cells and creates the error correction code for each of the memory cells based on the write data stored in the memory cells and the table.
11. The memory system of claim 10, wherein the table is such that numbers are allocated to the areas in ascending order of threshold voltage and the codes of the areas correspond to the numbers of the areas, and
the controller creates the error correction code for each of the memory cells based on the write data stored in the memory cells and the codes.
12. The memory system of claim 11, wherein the controller, if it determines in the error correction that the data is the same as that at the time of reception from the host device and has shifted to a different area, treats a memory cell that stores the data as a latent defective memory cell.
13. The memory system of claim 11, wherein the controller, if it detects more than a specific number of latent defective memory cells on more than one of the word lines comprised in the same erase block, moves all the data stored in the memory cells belonging to the same erase block to memory cells belonging to another erase block.
14. The memory system of claim 7, wherein the page comprises
a first area which stores write data provided by the host device, and
a second area which stores an error correction code encoded based on data stored in the first area.
15. A memory system comprising:
a memory module which comprises a plurality of nonvolatile memory cells with a plurality of pages and line-and-space word lines to which more than one of the memory cells are connected; and
a controller which receives write data from a host device,
creates an error correction code for each page based on the write data stored on a same page connected to a same word line,
creates a parity in units of one or more of the memory cells based on a threshold area of the write data stored in the memory cells,
adds the error correction code and the parity to the write data,
stores, on the pages in the memory module, the write data to which the error correction code and the parity have been added,
makes an error correction of the data to which the error correction code and the parity have been added, by using the error correction code, and
identifies the memory cell that has made an error by using the parity for the data to which the error correction code and the parity have been added when the error correction has failed.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A multi-cylinder internal-combustion engine comprising:
at least one intake valve and at least one exhaust valve for each cylinder, each provided with respective elastic return means that push the valve towards a closed position, for controlling respective intake pipes and exhaust pipes;
at least one camshaft for actuating the intake valves and the exhaust valves of the engine cylinders by means of respective tappets,
wherein each intake valve is controlled by the respective tappet, against the action of the aforesaid elastic return means, by interposition of hydraulic means including a pressurized-fluid chamber;
said pressurized-fluid chamber being designed to be connected by means of a solenoid valve to an exhaust channel in order to uncouple the intake valve from the respective tappet and cause fast closing of the valve as a result of the respective elastic return means; and
electronic control means for controlling each solenoid valve in such a way as to vary the time and the stroke of opening of the respective intake valve as a function of one or more operating parameters of the engine,
wherein said engine
has at least two different cylinders that have their respective intake strokes out of phase with respect to one another substantially by one complete revolution of the engine shaft;
wherein communication with the exhaust channel of the pressurized-fluid chambers associated to the intake valves of said two different cylinders is controlled by a single common solenoid valve,
wherein a main channel for supply of pressurized fluid is provided, communicating with the pressurized chambers associated to the intake valves of the two different cylinders of the engine via respective first non-return valves that enable the passage of fluid only in the direction of the pressurized-fluid chambers,
wherein the pressurized chambers associated to the intake valves of said two different cylinders of the engine are also directly connected to one another by a by-pass channel via two respective second non-return valves that enable the passage of fluid only from each of the two pressurized chambers towards said by-pass channel; and
wherein said by-pass channel is designed to be set in communication via the aforesaid single common solenoid valve with an exhaust channel common for the two pressurized chambers,
wherein associated to the two pressurized chambers associated to the intake valves of the aforesaid two different cylinders of the engine is a single common fluid accumulator that is in communication with said common exhaust channel,
wherein interposed in the main channel for supply of pressurized fluid is at least one fluid tank vented at the top to the atmosphere, having an inlet at its top for receiving the pressurized fluid, and an outlet on its bottom connected to the pressurized chambers via said first non-return valves, and
wherein said tank has a further outlet on its bottom communicating with said common exhaust channel.