1. An apparatus for performing cryptographic operations, comprising:
a cryptographic instruction, received by fetch logic in a microprocessor as part of an instruction flow executing on said microprocessor, wherein said cryptographic instruction is retrieved from memory and prescribes one of the cryptographic operations;
translation logic, operatively coupled to said cryptographic instruction, configured to translate said cryptographic instruction into micro instructions, wherein said micro instructions are ordered to direct said microprocessor to load a second input text block from said memory and to execute said one of the cryptographic operations on said second input text block prior to directing said computing device to store an output text block corresponding to a first input text block to said memory;
whereby said output text block is stored during execution of said one of the cryptographic operations on said second input text block.
2. The apparatus as recited in claim 1, wherein said one of the cryptographic operations comprises:
an encryption operation, said encryption operation comprising encryption of a plurality of plaintext blocks to generate a corresponding plurality of ciphertext blocks;
wherein said plurality of plaintext blocks comprise:
said first and second input text blocks; and
wherein said corresponding plurality of ciphertext blocks comprise:
said output text block.
3. The apparatus as recited in claim 1, wherein said one of the cryptographic operations comprises:
a decryption operation, said decryption operation comprising decryption of a plurality of ciphertext blocks to generate a corresponding plurality of plaintext blocks;
wherein said plurality of ciphertext blocks comprise:
said first and second input text blocks; and
wherein said corresponding plurality of plaintext blocks comprise:
said output text block.
4. The apparatus as recited in claim 1, further comprising:
execution logic, disposed within said microprocessor, operatively coupled to receive said micro instructions, configured to store said output text block while executing said one of the cryptographic operations on said second input text block.
5. The apparatus as recited in claim 4, wherein said execution logic comprises a cryptography unit.
6. The apparatus as recited in claim 5, wherein said cryptography unit is configured to execute said one of the cryptographic operations according to the Advanced Encryption Standard (AES).
7. The apparatus as recited in claim 5, wherein said cryptography unit comprises:
a 2-stage round engine, configured to pipeline execution of said first and second input text blocks.
8. The apparatus as recited in claim 1, wherein said micro instructions comprise:
a load micro instruction, configured to direct said microprocessor to load said second input text block and to execute said one of the cryptographic operations on said second input text block; and
a store micro instruction, configured to direct said microprocessor to store said output text block.
9. The apparatus as recited in claim 1, wherein said cryptographic instruction is prescribed according to the x86 instruction format.
10. The apparatus as recited in claim 1, wherein said cryptographic instruction implicitly references a plurality of registers within said microprocessor.
11. The apparatus as recited in claim 10, wherein said plurality of registers comprises:
a first register, wherein contents of said first register comprise a first pointer to a first memory address, said first memory address specifying a first location in memory for access of a plurality of input text blocks upon which said one of the cryptographic operations is to be accomplished, and wherein said plurality of input text blocks comprises said first and second input text blocks.
12. The apparatus as recited in claim 10, wherein said plurality of registers comprises:
a second register, wherein contents of said second register comprise a second pointer to a second memory address, said second memory address specifying a second location in said memory for storage of a corresponding plurality of output text blocks, said corresponding plurality of output text blocks being generated as a result of accomplishing said one of the cryptographic operations upon a plurality of input text blocks, and wherein said plurality of output text blocks comprise said output text block.
13. The apparatus as recited in claim 10, wherein said plurality of registers comprises:
a third register, wherein contents of said third register indicate a number of text blocks within a plurality of input text blocks.
14. The apparatus as recited in claim 10, wherein said plurality of registers comprises:
a fourth register, wherein contents of said fourth register comprise a third pointer to a third memory address, said third memory address specifying a third location in memory for access of cryptographic key data for use in accomplishing said one of the cryptographic operations.
15. The apparatus as recited in claim 10, wherein said plurality of registers comprises:
a fifth register, wherein contents of said fifth register comprise a fourth pointer to a fourth memory address, said fourth memory address specifying a fourth location in memory, said fourth location comprising said initialization vector location, contents of said initialization vector location comprising an initialization vector or initialization vector equivalent for use in accomplishing said one of the cryptographic operations.
16. The apparatus as recited in claim 10, wherein said plurality of registers comprises:
a sixth register, wherein contents of said sixth register comprise a fifth pointer to a fifth memory address, said fifth memory address specifying a fifth location in memory for access of a control word for use in accomplishing said one of the cryptographic operations, wherein said control word prescribes cryptographic parameters for said one of the cryptographic operations.
17. An apparatus for performing cryptographic operations, comprising:
fetch logic, disposed within a microprocessor, configured to fetch a cryptographic instruction from memory as part of an instruction flow executing on said microprocessor, said cryptographic instruction directing said microprocessor to perform one of the cryptographic operations; and
translation logic, configured to translate said cryptographic instruction into a sequence of micro instructions, said sequence of micro instructions comprising:
a first micro instruction, directing that a second input text block be loaded from said memory and that said one of the cryptographic operations be executed on said second input text block; and
a second micro instruction, directing that a first output text block be stored to said memory, said first output text block corresponding to a first input text block upon which said one of the cryptographic operations is executed;
wherein said translation logic issues said first micro instruction prior to issuing said second micro instruction;
whereby said output text block is stored during execution of said one of the cryptographic operations on said second input text block.
18. The apparatus as recited in claim 17, wherein said one of the cryptographic operations comprises:
an encryption operation, said encryption operation comprising encryption of a plurality of plaintext blocks to generate a corresponding plurality of ciphertext blocks;
wherein said plurality of plaintext blocks comprise:
said first and second input text blocks; and
wherein said corresponding plurality of ciphertext blocks comprise:
said output text block.
19. The apparatus as recited in claim 17, wherein said one of the cryptographic operations comprises:
a decryption operation, said decryption operation comprising decryption of a plurality of ciphertext blocks to generate a corresponding plurality of plaintext blocks;
wherein said plurality of ciphertext blocks comprise:
said first and second input text blocks; and
wherein said corresponding plurality of plaintext blocks comprise:
said output text block.
20. The apparatus as recited in claim 17, further comprising:
a cryptography unit, disposed within said microprocessor, operatively coupled to receive said micro instructions, and configured to store said output text block to said memory while executing said one of the cryptographic operations on said second input text block.
21. The apparatus as recited in claim 20, wherein said cryptography unit is configured to execute said one of the cryptographic operations according to the Advanced Encryption Standard (AES).
22. The apparatus as recited in claim 20, wherein said cryptography unit comprises:
a 2-stage round engine, configured to pipeline execution of said first and second input text blocks.
23. The apparatus as recited in claim 17, wherein said cryptographic instruction is prescribed according to the x86 instruction format.
24. A method for performing cryptographic operations, the method comprising:
within a microprocessor, fetching a cryptographic instruction from a memory as part of an instruction flow executing on the microprocessor; wherein the cryptographic instruction prescribes one of the cryptographic operations;
translating the cryptographic instruction into a first micro instruction and a second micro instruction, the first micro instruction directing the microprocessor to load a second input text block from the memory and to execute the one of the cryptographic operations on the second input text block, the second micro instruction directing the microprocessor to store a first output text block to the memory, where the first output text block corresponds to a first input text block upon which said the of the cryptographic operations is executed; and
issuing the first micro instruction to a cryptography unit within the microprocessor prior to issuing the second micro instruction to the cryptography unit;
whereby said issuing causes the output text block to be stored during execution of the one of the cryptographic operations on the second input text block.
25. The method as recited in claim 24, wherein said translating comprises:
via the first micro instruction, prescribing that an encryption operation be executed on the second text block to generate a corresponding second ciphertext block.
26. The apparatus as recited in claim 24, wherein said translating comprises:
via the first micro instruction, prescribing that a decryption operation be executed on the second text block to generate a corresponding second plaintext block.
27. The apparatus as recited in claim 24, further comprising:
executing the first and second micro instructions within the cryptography unit, wherein said executing comprises:
storing the output text block while performing the one of the cryptographic operations on the second input text block.
28. The apparatus as recited in claim 24, wherein the cryptographic instruction prescribes execution of the one of the cryptographic operations according to the Advanced Encryption Standard (AES).
29. The apparatus as recited in claim 24, further comprising:
executing the first and second micro instructions within the cryptography unit, wherein said executing comprises pipelining the first and second input text blocks through a 2-stage round engine.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for manufacturing a cathode slurry for use in a biocompatible battery comprising the steps of:
mixing one or more of a liquid phase pre-mixture with one or more of a solid phase pre-mixture into a cathode slurry mixture;
obtaining a laminar structure wherein the laminar structure has a volume removed to form a cavity;
filtering the cathode slurry mixture; and
distributing the cathode slurry mixture into the cavity of the laminar structure to form a biocompatible cathode for use in a biocompatible battery.
2. The method of claim 1 further comprising checking a quality of the solid phase pre-mixture and the liquid phase pre-mixture.
3. The method of claim 1 further comprising storing and recirculating the cathode slurry mixture after filtering the cathode slurry mixture.
4. The method of claim 1 further comprising drying the cathode slurry mixture.
5. The method of claim 1 wherein the liquid phase pre-mixture comprises one or more reagents wherein at least one reagent is a liquid phase reagent.
6. The method of claim 5 further comprising filtering the liquid phase reagents.
7. The method of claim 5 wherein one liquid phase reagent comprises a solvent.
8. The method of claim 7 wherein the solvent comprises toluene.
9. The method of claim 1 wherein the solid phase pre-mixture comprises one or more solid phase reagents.
10. The method of claim 9 further comprising sieving the solid phase reagents to a uniform particle size.
11. The method of claim 9 wherein the solid phase reagent comprises a jet milled electrolytic manganese dioxide.
12. The method of claim 9 wherein one solid phase pre-mixture comprises a transition metal oxide.
13. The method of claim 12 wherein the transition metal oxide comprises manganese dioxide.
14. The method of claim 9 wherein one solid phase reagent comprises a carbon allotrope.
15. The method of claim 14 wherein the carbon allotrope comprises graphite.
16. The method of claim 15 wherein the graphite comprises carbon black.
17. The method of claim 5 wherein the liquid phase pre-mixture comprises a hydrophobic binder.
18. The method of claim 17 wherein the hydrophobic binder comprises polyisobutylene (PIB).
19. The method of claim 17 wherein the hydrophobic binder comprises a fluorocarbon solid.
20. The method of claim 19 wherein the fluorocarbon solid comprises polytetrafluoroethylene (PTFE).
21. A method for manufacturing a biocompatible cathode for use in a biocompatible battery comprising the steps of:
obtaining toluene, manganese dioxide, carbon black, and polyisobutylene;
filtering toluene;
sieving manganese dioxide;
sieving carbon black;
sieving polyisobutylene;
mixing the toluene and the polyisobutylene into a liquid phase pre-mixture;
mixing the manganese dioxide and carbon black into a solid phase pre-mixture;
checking a quality of both the solid and liquid phase pre-mixtures
mixing the solid phase pre-mixture and liquid phase pre-mixture into a cathode slurry mixture;
filtering the cathode slurry mixture;
storing the cathode slurry mixture;
recirculating the cathode slurry mixture;
obtaining a laminar structure wherein the laminar structure has a volume removed to form a cavity;
filtering the stored cathode slurry mixture;
distributing the filtered cathode slurry mixture into the cavity of the laminar structure; and
drying the cathode slurry mixture to form a biocompatible cathode for use in a biocompatible battery.
22. A method for manufacturing a cathode slurry for use in a biomedical device comprising comprising the steps of:
mixing one or more of a liquid phase pre-mixture with one or more of a solid phase pre-mixture into a cathode slurry mixture;
obtaining a laminar structure wherein the laminar structure has a volume removed to form a cavity;
filtering the cathode slurry mixture; and
distributing the cathode slurry mixture into the cavity of the laminar structure forming the cathode slurry for use in a biomedical device;
wherein the biomedical device comprises an insert device comprising:
an electroactive element responsive to a controlling voltage signal;
a biocompatible battery;
wherein the biocompatible battery comprises:
a first and second electrode;
an anode;
a separator;
a laminar structure, wherein at least one layer of the laminar structure has a volume removed to form a cavity; and
the cathode slurry wherein at least an average molecular size of one component of the cathode slurry is reduced in particle size by milling said component; and
wherein the cathode slurry is capable of filling the cavity, based on its rheology, while maintaining electroconductivity through the laminar structure in the cavity; and
a circuit electrically connected to a biocompatible battery, wherein the circuit provides the controlling voltage signal.
23. The method of claim 22 wherein the biomedical device is a contact lens.
24. A method of manufacturing a cathode slurry mixture for use in a biomedical device comprising the steps of:
mixing one or more of a liquid phase pre-mixture with one or more of a solid phase pre-mixture into a cathode slurry mixture;
obtaining a laminar structure wherein the laminar structure has a volume removed to form a cavity;
filtering the cathode slurry mixture; and
distributing the cathode slurry mixture into the cavity of the laminar structure forming the cathode slurry mixture for use in a biomedical device;
wherein the biomedical device comprises:
an insert device comprising:
an electroactive element responsive to a controlling voltage signal;
a biocompatible battery;
wherein the biocompatible battery comprises:
a first and second electrode;
an anode;
a separator; and
the cavity for storing a cathode mixture;
wherein the cathode mixture is capable for storage, based on its rheology, while maintaining electroconductivity and biocompatibility;
wherein the cathode slurry mixture comprises:
\u2003manganese dioxide;
\u2003graphite;
\u2003polyisobutylene (PIB);
\u2003Toluene; and
wherein at least an average molecular size of one component of the cathode mixture is reduced in particle size by milling said component; and
a circuit electrically connected to the biocompatible battery wherein the circuit provides the controlling voltage signal.