1. A storage device for protecting content, comprising:
a memory device; and
a controller that controls the memory device to store encrypted content, a control file for controlling usage of the encrypted content, a security information file including information on the control file, and a title key needed for decryption of the encrypted content,
wherein the storage device is configured to send the security information file, the control file, the encrypted content and the title key to a host device, and the security information file includes an identifier indicating where the control file is stored in the storage device,
wherein the security information file, the control file, and the encrypted content are stored and sent as separate files, and
wherein the security information file further includes an initialization vector which is a value used in an encryption algorithm, the encrypted content is generated by encrypting content using the initialization vector, and the encrypted content is decrypted using the initialization vector.
2. The storage device of claim 1, wherein the security information file further includes a name of the control file.
3. The storage device of claim 1, wherein the security information file has a same name as a name of the encrypted content.
4. The storage device of claim 1, wherein the identifier includes an address where the control file is stored.
5. The storage device of claim 1, wherein the security information file has a first filename extension and the control file has a second filename extension different from the first filename extension.
6. A host device for protecting content, comprising:
a content recording device configured to:
write a control file for controlling usage of encrypted content to a storage device;
read an address of a protected area in the storage device, wherein access to the protected area is available after passing authentication;
write a title key needed for decryption of the encrypted content to the protected area at the read address;
write the encrypted content to the storage device; and
write, to the storage device, a security information file including information an identifier indicating where the control file is stored in the storage device,
wherein the security information file, the control file, and the encrypted content are stored as separate files in the storage device, and
wherein the security information file further includes an initialization vector which is a value used in an encryption algorithm, the encrypted content is generated by encrypting content using the initialization vector, and the encrypted content is decrypted using the initialization vector.
7. The host device of claim 6, wherein the security information file further includes a name of the control file.
8. The host device of claim 6, wherein the security information file has a same name as a name of the encrypted content.
9. The host device of claim 6, wherein the identifier includes an address where the control file is stored.
10. The host device of claim 6, wherein the security information file has a first filename extension and the control file has a second filename extension different from the first filename extension.
11. A host device for protecting content, comprising:
a content decryption device configured to:
read a security information file including information in a control file from a storage device;
read the control file for controlling usage of encrypted content from the storage device using the security information file;
read the encrypted content from the storage device; and
decrypt the encrypted content,
wherein the security information file includes an identifier indicating where the control file is stored in the storage device,
wherein the security information file, the control file, the encrypted content and a title key needed for decryption of the encrypted content are stored in the storage device,
wherein the security information file, the control file and the encrypted content are stored and read as separate files, and
wherein the security information file further includes an initialization vector which is a value used in an encryption algorithm, the encrypted content is generated by encrypting content using the initialization vector, and the encrypted content is decrypted using the initialization vector.
12. The host device of claim 11, wherein the security information file further includes a name of the control file.
13. The host device of claim 11, wherein the security information file has a same name as a name of the encrypted content.
14. The host device of claim 11, wherein the identifier includes an address where the control file is stored.
15. The host device of claim 11, wherein the security information file has a first filename extension and the control file has a second filename extension different from the first filename extension.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of mitigating soft errors in an asynchronous digital circuit having a stage comprising duplicate asynchronous circuit elements, each of said duplicate asynchronous digital circuit elements having at least one input terminal and at least one output terminal, each of said duplicate asynchronous digital circuit elements providing the same logic operation, comprising the steps of:
(a) asserting a digital signal at corresponding ones of each of said at least one input terminals of said duplicate asynchronous digital circuit elements;
(b) inhibiting a variation of said asserted digital signal asserted at corresponding ones of each of said at least one input terminals of said duplicate asynchronous digital circuit elements;
(c) comparing an output signal appearing at said at least one output terminal of one of said duplicate asynchronous digital circuit elements with a corresponding output signal appearing at said at least one output terminal of the other of said duplicate asynchronous digital circuit elements; and
based on the result of the comparison of the output signals:
(d) if said output signals are not deemed equivalent:
(1) inhibiting a resultant signal from being provided as output from the stage;
(2) maintaining the step of inhibiting a variation of said asserted digital signal asserted at corresponding ones of each of said at least one input terminals of said duplicate asynchronous digital circuit elements;
(3) continuing to compare an output signal appearing at said at least one output terminal of one of said duplicate asynchronous digital circuit elements with a corresponding output signal appearing at said at least one output terminal of the other of said duplicate asynchronous digital circuit elements; and
(4) continuing steps (d)(1), (d)(2) and (d)(3) until said output signals are deemed equivalent; and
(e) if said output signals are deemed equivalent:
(1) providing at least one resultant signal as output from the stage; and
(2) permitting a variation of the asserted digital signal asserted at corresponding ones of each of said at least one input terminals of said duplicate
asynchronous digital circuit elements;
whereby the stage comprising duplicate asynchronous digital circuit elements is active in the absence of soft errors and is prevented from being active during the presence of soft errors, thereby eliminating soft errors from propagating in the asynchronous digital circuit.
2. The method of mitigating soft errors in an asynchronous digital circuit having a stage comprising duplicate asynchronous circuit elements of claim 1, wherein said method employs three or more stages comprising duplicate asynchronous circuit elements.
3. The method of mitigating soft errors in an asynchronous digital circuit having a stage comprising duplicate asynchronous circuit elements of claim 1, wherein the step of comparing an output signal appearing at said at least one output terminal of one of said duplicate asynchronous digital circuit elements with a corresponding output signal appearing at said at least one output terminal of the other of said duplicate asynchronous digital circuit elements is performed by a c-element.
4. The method of mitigating soft errors in an asynchronous digital circuit having a stage comprising duplicate asynchronous circuit elements of claim 1, wherein the step of inhibiting a variation of said asserted digital signal asserted at corresponding ones of each of said at least one input terminals of said duplicate asynchronous digital circuit elements is performed by a c-element.
5. The method of mitigating soft errors in an asynchronous digital circuit having a stage comprising duplicate asynchronous circuit elements of claim 1, wherein the step of inhibiting a resultant signal from being provided as output from the stage is performed by a c-element.
6. The method of mitigating soft errors in an asynchronous digital circuit having a stage comprising duplicate asynchronous circuit elements of claim 1, wherein said method corrects a plurality of soft errors using a weak c-element.
7. An asynchronous digital circuit configured to mitigate soft error propagation, comprising:
a stage comprising duplicate asynchronous circuit elements, each of said duplicate asynchronous digital circuit elements having at least one input terminal and at least one output terminal, each of said duplicate asynchronous digital circuit elements providing the same logic operation;
a first comparison element having two input terminals and a first output, a selected one of said two input terminals connected to each of said at least one output terminal of each of said duplicate asynchronous digital circuit elements, and a second comparison element having two input terminals and a second output, a selected one of said two input terminals connected to each of said at least one output terminal of each of said duplicate asynchronous digital circuit elements; and
a control element in electrical communication with said first output of said first comparison element and said second output of said second comparison element, said control element configured to provide control signals based on the equivalence or lack of equivalence of signals appearing at said first output of said first comparison element and said second output of said second comparison element:
in the event that the signals appearing at said first and second outputs are not equivalent:
said control element provides a control signal to inhibit a resultant signal from appearing as output at an output terminal of the stage; and
said control element provides a control signal to inhibit a variation of said asserted digital signal asserted at corresponding ones of each of said at least one input terminals of said duplicate asynchronous digital circuit elements; and
in the event that the signals appearing at said first and second outputs are equivalent:
said control element provides a control signal to allow at least one resultant signal as output at said output terminal the stage; and
said control element provides a control signal to permit a variation of the asserted digital signal asserted at corresponding ones of each of said at least one input terminals of said duplicate asynchronous digital circuit elements;
so that the stage comprising duplicate asynchronous digital circuit elements is active to provide a signal representing said logic operation in the absence of soft errors and is prevented from being active during the presence of soft errors, thereby eliminating soft errors from propagating in the asynchronous digital circuit.
8. The asynchronous digital circuit configured to mitigate soft error propagation of claim 7, wherein said asynchronous digital circuit comprises three or more stages comprising duplicate asynchronous circuit elements.
9. The asynchronous digital circuit configured to mitigate soft error propagation of claim 7, wherein said first comparison element is a c-element.
10. The asynchronous digital circuit configured to mitigate soft error propagation of claim 7, wherein said control element is combined with said comparison element.
11. The asynchronous digital circuit configured to mitigate soft error propagation of claim 7, wherein said circuit is a field programmable gate array.
12. The asynchronous digital circuit configured to mitigate soft error propagation of claim 7, wherein said circuit comprises dual interlocked programmable bits.
13. The asynchronous digital circuit configured to mitigate soft error propagation of claim 7, wherein said circuit comprises a pre-charged half buffer.
14. The asynchronous digital circuit configured to mitigate soft error propagation of claim 7, wherein said circuit comprises a weak c-element.