1. An input buffer, comprising:
a main input transistor pair that receives a voltage input;
a tail current source; and
a squeezable tail current source circuit coupled to the main input transistor pair and to the tail current source, the squeezable tail current source circuit including a single-ended self-biased folded feedback loop,
wherein the main input transistor pair, the tail current source, and the squeezable tail current source circuit are configured such that current through the main input transistor pair is maintained as the voltage input varies.
2. The input buffer of claim 1, wherein the folded feedback loop comprises:
a folding transistor; and
a biasing current source that biases the folding transistor.
3. The input buffer of claim 2, wherein the squeezable tail current source circuit further includes:
a replica transistor pair coupled to the tail current source and the folding transistor that replicates the main input transistor pair and receives the voltage input;
a bias transistor coupled to the replica transistor pair, the folding transistor, and the biasing current source; and
a tail transistor pair coupled to the bias transistor, the folding transistor, and the biasing current source,
wherein the biasing current source and the folding transistor isolate the bias transistor and the tail transistor pair from a drain voltage of the replica transistor pair.
4. The input buffer of claim 3, wherein current through the tail transistor pair and the bias transistor is squeezed as the voltage input to the main input transistor pair is decreased, thereby increasing a gate voltage of the bias transistor, and thereby causing current through both the replica transistor pair and the main input transistor pair to remain nearly constant.
5. The input buffer of claim 3, wherein an input to the replica transistor pair is scaled independently to meet different bandwidth requirements for settling.
6. The input buffer of claim 3, wherein the main input transistor pair, the replica transistor pair, the tail transistor pair, and the bias transistor are NMOS transistors.
7. The input buffer of claim 3, wherein the main input transistor pair, the replica transistor pair, the tail transistor pair, and the bias transistor are PMOS transistors.
8. The input buffer of claim 2, wherein the folding transistor is an NMOS transistor.
9. The input buffer of claim 2, wherein the folding transistor is a PMOS transistor.
10. A differential input buffer, comprising:
a first main input transistor pair that receives a first voltage input;
a second main input transistor pair that receives a second voltage input;
a first tail current source;
a second tail current source;
a first squeezable tail current source circuit coupled to the first main input transistor pair and to the first tail current source, the first squeezable tail current source circuit including a first single-ended self-biased folded feedback loop;
a second squeezable tail current source circuit coupled to the second main input transistor pair and to the second tail current source, the second squeezable tail current source circuit including a second single-ended self-biased folded feedback loop,
wherein the first main input transistor pair, the first tail current source, and the first squeezable tail current source circuit are configured such that current through the first main input transistor pair is maintained as the first voltage input varies; and
wherein the second main input transistor pair, the second tail current source, and the second squeezable tail current source circuit are configured such that current through the second main input transistor pair is maintained as the second voltage input varies.
11. The differential input buffer of claim 10, wherein the first folded feedback loop comprises:
a first folding transistor; and
a first biasing current source that biases the first folding transistor.
12. The differential input buffer of claim 11, wherein the first squeezable tail current source circuit further includes:
a replica transistor pair coupled to the first tail current source and the first folding transistor that replicates the first main input transistor pair and receives the first voltage input;
a bias transistor coupled to the replica transistor pair, the first folding transistor, and the first biasing current source; and
a tail transistor pair coupled to the bias transistor, the first folding transistor, and the first biasing current source,
wherein the first biasing current source and the first folding transistor isolate the bias transistor and the tail transistor pair from a drain voltage of the replica transistor pair.
13. The differential input buffer of claim 12, wherein current through the tail transistor pair and the bias transistor is squeezed as the first voltage input to the first main input transistor pair is decreased, thereby increasing a gate voltage of the bias transistor, and thereby causing current through both the replica transistor pair and the first main input transistor pair to remain nearly constant.
14. The differential input buffer of claim 12, wherein the first main input transistor pair, the replica transistor pair, the tail transistor pair, and the bias transistor are NMOS transistors.
15. The differential input buffer of claim 12, wherein the first main input transistor pair, the replica transistor pair, the tail transistor pair, and the bias transistor are PMOS transistors.
16. The differential input buffer of claim 11, wherein the first folding transistor is an NMOS transistor.
17. The differential input buffer of claim 11, wherein the first folding transistor is a PMOS transistor.
18. The differential input buffer of claim 10, wherein the second folded feedback loop comprises:
a second folding transistor; and
a second biasing current source that biases the second folding transistor.
19. The differential input buffer of claim 18, wherein the second squeezable tail current source circuit further includes:
a replica transistor pair coupled to the second tail current source and the second folding transistor that replicates the second main input transistor pair and receives the second voltage input;
a bias transistor coupled to the replica transistor pair, the second folding transistor, and the second biasing current source; and
a tail transistor pair coupled to the bias transistor, the second folding transistor, and the second biasing current source,
wherein the second biasing current source and the second folding transistor isolate the bias transistor and the tail transistor pair from a drain voltage of the replica transistor pair.
20. The differential input buffer of claim 19, wherein current through the tail transistor pair and the bias transistor is squeezed as the second voltage input to the second main input transistor pair is decreased, thereby increasing a gate voltage of the bias transistor, and thereby causing current through both the replica transistor pair and the second main input transistor pair to remain nearly constant.
21. The differential input buffer of claim 19, wherein the second main input transistor pair, the replica transistor pair, the tail transistor pair, and the bias transistor are NMOS transistors.
22. The differential input buffer of claim 19, wherein the second main input transistor pair, the replica transistor pair, the tail transistor pair, and the bias transistor are PMOS transistors.
23. The differential input buffer of claim 18, wherein the second folding transistor is an NMOS transistor.
24. The differential input buffer of claim 18, wherein the second folding transistor is a PMOS transistor.
25. The differential input buffer of claim 10, further comprising:
a first stage having an input coupled to the first and second main input transistor pairs and having an output;
a second stage having an input coupled to the first stage output and having an output; and
an output coupled to the second stage output.
26. A method of maintaining a constant current through a main input transistor pair of a differential amplifier while maintaining high linearity, the method comprising:
providing a voltage input to the main input transistor pair;
mirroring a tail current to that of the current through the main input transistor pair by using a squeezable tail current source configured to isolate a bias transistor and a first transistor pair of the squeezable tail current source from a drain voltage of a second transistor pair of the squeezable tail current source, thereby causing the second transistor pair and the main input transistor pair to have a common drain bias; and
squeezing the tail current as the voltage input is decreased, thereby increasing a gate voltage of the bias transistor and allowing current through the main input differential pair to remain nearly constant.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An ORing element for use in a power supply, the ORing element comprising:
a field effect transistor (FET) for electrical connection between an output of the power supply and a bus;
a first bi-polar transistor, wherein an emitter of the first bi-polar transistor is electrically connected to a source of the FET, and wherein a collector of the first bi-polar transistor is electrically connected to a gate of the FET; and
a second bi-polar transistor, wherein an emitter of the second bi-polar transistor is electrically connected to a base of the second bi-polar transistor and a base of the first bi-polar transistor, and wherein a collector of the second bi-polar transistor is electrically connected to a drain of the FET.
2. The ORing element of claim 1, wherein the collector of the first bi-polar transistor is electrically connected to a first bias current.
3. The ORing element of claim 1, wherein the emitter of the second bi-polar transistor is electrically connected to a second bias current.
4. The ORing element of claim 1, wherein the first bi-polar transistor and the second bi-polar transistor are contained in a single package.
5. The ORing element of claim 4, wherein the single package is a 6-pin SOT-23 package.
6. A power system comprising:
a first power supply module;
a common power bus; and
an ORing element connected between the first power supply module and the common power bus, wherein the ORing element comprises:
a field effect transistor (FET) electrically connected between the first power supply module and the common power bus;
a first bi-polar transistor, wherein an emitter of the first bi-polar transistor is electrically connected to a source of the FET, and wherein a collector of the first bi-polar transistor is electrically connected to a gate of the FET; and
a second bi-polar transistor, wherein an emitter of the second bi-polar transistor is electrically connected to a base of the second bi-polar transistor and a base of the first bi-polar transistor, and wherein a collector of the second bi-polar transistor is electrically connected to a drain of the FET.
7. The power system of claim 6, wherein the collector of the first bi-polar transistor is electrically connected to a first bias current.
8. The power system of claim 6, wherein the emitter of the second bi-polar transistor is electrically connected to a second bias current.
9. The power system of claim 6, wherein the first bi-polar transistor and the second bi-polar transistor are contained in a single package.
10. The power system of claim 9, wherein the single package is a 6-pin SOT-23 package.
11. The power system of claim 6, further comprising a second power supply module;
and a second ORing element connected between the second power supply module and the common power bus.