1. An on-chip test circuit for testing an on-chip power switch coupled to a core logic and to a decoupling capacitance, the on-chip test circuit comprising:
a flip-flop, for serially receiving, registering and serially outputting test patterns;
a mode selector, coupled to the power switch and the flip-flop, for controlling operation mode of the power switch according to a test indication signal, the test indication signal indicates whether the power switch is in test mode or not; and
a voltage level control circuit, coupled to the decoupling capacitance, for controlling voltage level of the decoupling capacitance;
wherein under test mode, the mode selector selects the test patterns serially output from the flip-flop into the power switch and the voltage level control circuit pre-charges or discharges the decoupling capacitance, so that the voltage level of the decoupling capacitance is analyzed for determining whether the power switch is passed or failed.
2. The on-chip test circuit of claim 1, further comprising:
a test result isolation element, coupled to the voltage level control circuit and the decoupling capacitance, for outputting test result provided by the power switch under test and for blocking test result test result provided by other power switches not being under test when the on-chip test circuit are used to test a plurality of power switches in multiple power domain.
3. The on-chip test circuit of claim 1, wherein the mode selector has:
a control terminal for receiving the test indication signal;
a first input terminal for receiving a power switch control signal;
a second input terminal for receiving the test patterns output from the flip-flop; and
an output terminal for coupling to the power switch and the voltage level control circuit;
wherein,
when the test indication signal indicates the power switch being under normal mode, the mode selector outputs the power switch control signal to the power switch; and
when the test indication signal indicates the power switch being under test mode, the mode selector outputs the test patterns from the flip-flop to the power switch.
4. The on-chip test circuit of claim 1, wherein the power switch includes a header type power switch and the voltage level control circuit is a discharge circuit for discharging charges in the decoupling capacitance.
5. The on-chip test circuit of claim 4, wherein the voltage level control circuit includes:
a logic gate, receiving a discharge signal and the output from the mode selector; and
a MOS transistor, coupled to the decoupling capacitance, for discharging the decoupling capacitance under control of an output from the logic gate.
6. The on-chip test circuit of claim 1, wherein the power switch includes a footer type power switch and the voltage level control circuit is a pre-charge circuit for pre-charging the decoupling capacitance.
7. The on-chip test circuit of claim 6, wherein the voltage level control circuit includes:
a logic gate, receiving a pre-charge signal and the output from the mode selector; and
a MOS transistor, coupled to the decoupling capacitance, for pre-charging the decoupling capacitance under control of an output from the logic gate.
8. The on-chip test circuit of claim 1, wherein:
the power switch includes a footer type power switch and a header type power switch; and
the voltage level control circuit includes a pre-charge circuit for pre-charging the decoupling capacitance and a discharge circuit for discharging the decoupling capacitance.
9. An on-chip test method for testing an on-chip power switch coupled to a core logic and to a decoupling capacitance, the on-chip test method comprising:
controlling the power switch to enter a test mode under control of a test indication signal;
controlling charges stored in the decoupling capacitance;
controlling the power switch under control of test patterns; and
analyzing a voltage level at the decoupling capacitance for determining whether the power switch is passed or failed.
10. The on-chip test method of claim 9, wherein the power switch includes a header type power switch.
11. The on-chip test method of claim 10, wherein when the header type power switch being under ON test, the test method further comprising:
turning off the power switch, before the step of controlling charges stored in the decoupling capacitance;
turning on the power switch, before the analyzing step; and
the step of controlling charges stored in the decoupling capacitance comprising discharging charges stored in the decoupling capacitance.
12. The on-chip test method of claim 10, when the header type power switch being under OFF test, the test method further comprising:
turning off the power switch, before the step of controlling charges stored in the decoupling capacitance;
the step of controlling charges stored in the decoupling capacitance comprising discharging charges stored in the decoupling capacitance; and
the step of analyzing comprising measuring a leakage current flowing through the power switch.
13. The on-chip test method of claim 9, wherein the power switch includes a footer type power switch.
14. The on-chip test method of claim 13, wherein when the footer type power switch being under ON test, the test method further comprising:
turning off the power switch, before the step of controlling charges stored in the decoupling capacitance;
turning on the power switch, before the analyzing step; and
the step of controlling charges stored in the decoupling capacitance comprising pre-charging charges stored in the decoupling capacitance.
15. The on-chip test method of claim 13, wherein when the footer type power switch being under OFF test, the test method further comprising:
turning off the power switch, before the step of controlling charges stored in the decoupling capacitance;
the step of controlling charges stored in the decoupling capacitance comprising pre-charging charges stored in the decoupling capacitance; and
the step of analyzing comprising measuring a leakage current flowing through the power switch.
16. The on-chip test method of claim 9, wherein the power switch includes a header type power switch and a footer type power switch.
17. The on-chip test method of claim 16, wherein further comprising:
turning on one of the header type power switch and the footer type power switch when testing the other one.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for determining a location of an improved carrier signal emitted from a base station relative to a position of a communication device, the carrier signal having a signal strength and the communication device receiving signal strength information of the carrier signal from an operating wireless communications network, the method comprising the steps of:
receiving information of a signal strength at an adjacent location, wherein the adjacent location is determined by performing a lookup on a digital map, the receiving further comprising determining if the signal strength at the adjacent location is greater than the signal strength at a current location of the communication device, and if the signal strength of the adjacent location is less that of the signal strength at the current location, then locating a next adjacent grid reference in a 360 degree radius from the communication device; and
in response the received information of an improved signal strength being received at the adjacent location, displaying a direction of a position of the adjacent location on the communication device.
2. A method as claimed in claim 1 wherein the digital map comprises a grid reference depicting a location of a base station and geographical terrain.
3. A method as claimed in claim 1 wherein the digital map further comprises a signal strength emitted by the base station at a grid reference.
4. A method as claimed in claim 3, wherein the digital map further comprises statistical data comprising refraction and deflection characteristics of the terrain and an effect the statistical data has on the carrier signal strength at the grid reference.
5. A method as claimed in claim 1 wherein the digital map is maintained by a service provider.
6. A method as claimed in claim 5 wherein the digital map is requested from the service provider and stored on the communication device.
7. A method as claimed in claim 1 wherein an icon displays the direction of the adjacent location having improved signal strength on a display of the communication device.
8. A method as claimed in claim 7 wherein the icon is a signal strength direction indicator.
9. A method as claimed in claim 1 wherein a graphical map displays the direction of the adjacent location of the improved signal strength on the communication device.
10. A method as claimed in claim 1 wherein in response to an improved signal strength at the adjacent location, returning a ranked list of adjacent locations of improved signal strengths.
11. A system for determining a location of an improved carrier signal emitted from a base station relative to a position of a communication device, the carrier signal having a signal strength and the communication device receiving signal strength information of the carrier signal from an operating wireless communications network, the system comprising:
means for receiving information of a signal strength at an adjacent location, wherein the adjacent location is determined by performing a lookup on a digital map, wherein the means for receiving comprises means for determining if the signal strength at the adjacent location is greater than the signal strength at a current location of the communication device, and if the signal strength of the adjacent location is less that of the signal strength at the current location, then locating a next adjacent grid reference in a 360 degree radius from the communication device; and
in response the received information of an improved signal strength being received at the adjacent location, means for displaying a direction of a position of the adjacent location on the communication device.
12. A system as claimed in claim 11 wherein the digital map comprises a grid reference depicting a location of a base station and geographical terrain.
13. A system as claimed in claim 11 wherein the digital map further comprises a signal strength emitted by the base station at a grid reference.
14. A system as claimed in claim 12, wherein the digital map further comprises statistical data comprising refraction and deflection characteristics of the terrain and an effect the statistical data has on the signal strength at the grid reference.
15. A system as claimed in claim 11 wherein the digital map is maintained by a service provider.
16. A system as claimed in claim 15 wherein the digital map is requested from the service provider and stored on the communication device.
17. A system as claimed in claim 11 wherein an icon displays the direction of the adjacent location having improved signal strength on a display of the communication device.
18. A system as claimed in claim 17 wherein the icon is a signal strength direction indicator.
19. A system as claimed in claim 11 wherein a graphical map displays the direction of the adjacent location of the improved signal strength on the communication device.
20. A system as claimed in claim 11 further comprising means for returning a ranked list of adjacent locations of improved signal strengths, in response to an improved signal strength at the adjacent location.
21. A computer program product loadable into the internal memory of a digital computer, comprising software code portions for performing, when said product is run on a computer, the method of claim 1.
22. A service for determining a location of an improved carrier signal emitted from a base station relative to a position of a communication device, the carrier signal having a signal strength and the communication device receiving signal strength information of the carrier signal from an operating wireless communications network, the service comprising the steps of:
receiving information of a signal strength at an adjacent location, wherein the adjacent location is determined by performing a lookup on a digital map, the receiving further comprising determining if the signal strength at the adjacent location is greater than the signal strength at a current location of the communication device, and if the signal strength of the adjacent location is less that of the signal strength at the current location, then locating a next adjacent grid reference in a 360 degree radius from the communication device; and
in response to the received information of an improved signal strength being received at the adjacent location, displaying a direction of a position of the adjacent location on the communication device.