1. A power converter, comprising:
an energy-transfer reactance comprising at least one inductor, and operating at a primary AC magnetic field frequency which is less than half of the reactance’s resonant frequency;
a link switch, connected across said reactance in a crowbar configuration which includes a resistance element which is connected to dissipate energy stored in said reactance when said link switch is on;
an input switch array configured to drive AC current through said reactance; and
an output network switch array connected to extract energy from said reactance;
wherein said input switch array performs at least two drive operations, in the same direction but from different sources, during a single half-cycle of said reactance;
wherein said energy-transfer reactance comprises an inductor paralleled with a capacitor;
and wherein, when said link switch is on, said switch arrays are connected to totally disconnect said reactance from a power input and a power output of the converter.
2. The converter of claim 1, wherein said switch arrays are full-bridge arrays.
3. The converter of claim 1, wherein said reactance comprises a transformer.
4. A power converter, comprising:
an energy-transfer reactance comprising at least one inductor, and operating at a primary AC magnetic field frequency which is less than half of the reactance’s resonant frequency;
a link switch, connected across said reactance in a crowbar configuration which includes a resistance element which is connected to dissipate energy stored in said reactance when said link switch is on;
an input switch array configured to drive current through said reactance; and
an output switch array to extract energy from said reactance;
wherein said input switch array performs at least two different drive operations at different times during a single cycle of said reactance,
wherein said output switch array performs at least two different drive operations at different times during a single cycle of said reactance;
wherein said energy-transfer reactance comprises an inductor paralleled with a capacitor; and
wherein, when said link switch is on, said switch arrays are connected to totally disconnect said energy-transfer reactance from a power input and a power output of the converter.
5. The converter of claim 4, wherein said switch arrays are full-bridge arrays.
6. The converter of claim 4, wherein said input switch array connects said reactance to said power input which is shunted by a capacitor which provides a low-impedance voltage source thereat.
7. The converter of claim 4, wherein said reactance comprises a transformer.
8. A method for operating a power converter, comprising the actions of:
driving an energy-transfer reactance with a full AC waveform, at a base frequency which is less than half the resonant frequency of said reactance;
coupling power into said reactance, on each cycle thereof, with two different drive phases, respectively supplied from two different legs of a polyphase power input; and
coupling power out of said reactance, on each cycle thereof, with two different connection phases, respectively driving two different legs of a polyphase power output; and
under at least some overvoltage conditions, disconnecting said reactance from said power input or said power output or both, while also dumping energy from said reactance through a link switch which shunts said reactance;
wherein said energy-transfer reactance comprises an inductor paralleled with a capacitor; and
wherein, when said link switch is on, an input switch array and an output switch array are connected to totally disconnect said reactance from said power input and said power output.
9. The method of claim 8, wherein said switch arrays are symmetrically connected to said energy-transfer reactance.
10. The method of claim 8, wherein said energy-transfer reactance comprises a transformer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A pad area, comprising:
a substrate;
an embossed layer having an embossed pattern disposed on the substrate;
an interconnection layer disposed on the embossed layer and covering at least the embossed pattern of the embossed layer; and
a passivation layer surrounding an edge of the interconnection layer.
2. The pad area as claimed in claim 1, further comprising a conductive ball disposed on the interconnection layer.
3. The pad area as claimed in claim 1, further comprising a gate electrode pattern disposed between the substrate and the embossed layer.
4. The pad area as claimed in claim 1, further comprising at least one of a first electrode pattern, a second electrode pattern, and a reflective layer pattern disposed on the interconnection layer.
5. The pad area as claimed in claim 1, wherein the embossed layer is formed of a single embossed pattern.
6. The pad area as claimed in claim 1, wherein the embossed layer is formed of at least two embossed patterns.
7. The pad area as claimed in claim 1, wherein the embossed layer is portions of an interlayer insulating layer and a gate insulating layer.
8. The pad area as claimed in claim 1, wherein the embossed layer is formed of at least one of a silicon layer, a gate electrode layer, a gate electrode, and an interlayer insulating layer.
9. The pad area as claimed in claim 1, wherein the interconnection layer is flat when the embossed layer thereunder is formed of a single embossed pattern.
10. The pad area as claimed in claim 1, wherein the interconnection layer is uneven when the embossed layer thereunder is formed of at least two embossed patterns.
11. The pad area as claimed in claim 1, wherein the interconnection layer is higher than the passivation layer.
12. The pad area as claimed in claim 1, wherein the interconnection layer is a portion of at least one of source and drain electrodes and a gate electrode.
13. The pad area as claimed in claim 1, wherein the passivation layer is a portion of a planarization layer or a pixel defining layer.
14. A method of fabricating a pad area, comprising:
forming a substrate;
forming a gate insulating layer and an interlayer insulating layer on the substrate, and patterning the layers to form an embossed layer;
depositing source and drain electrode materials on the substrate having the embossed layer, and then patterning the electrode materials to form an interconnection layer covering at least the embossed layer; and
forming a passivation layer covering an edge of the interconnection layer.
15. The method as claimed in claim 14, further comprising, before forming the gate insulating layer,
depositing a gate electrode material on the substrate, and then patterning the gate electrode material to form a gate electrode pattern.
16. The method as claimed in claim 14, further comprising, after forming the passivation layer,
forming an auxiliary interconnection layer on the interconnection layer and the passivation layer.
17. A method of fabricating a pad area, comprising:
preparing a substrate;
forming a semiconductor layer pattern on the substrate;
forming a gate insulating layer on the substrate having the semiconductor layer pattern;
forming a gate electrode pattern on the gate insulating layer;
forming an embossed pattern having a width larger than the gate electrode pattern on the substrate having the gate electrode pattern;
forming source and drain electrode materials on the substrate having the embossed pattern, and then patterning the electrode materials to form an interconnection layer covering at least the embossed pattern; and
forming a passivation layer covering an edge of the interconnection layer.
18. The method as claimed in claim 17, further comprising, after forming the passivation layer,
forming an auxiliary interconnection layer on the interconnection layer and the passivation layer.