1. A boundary scan cell for use in a circuit having a boundary scan shift register (BSSR) having boundary scan cells, each boundary scan cell being associated with a predetermined pin of said circuit and comprising:
a single-bit shift register element that outputs a bit value;
an update latch associated with said single-bit shift register element, said update latch latching said bit value to control the logic state of the pin associated with said boundary scan cell;
analog switches connecting the pin associated with said boundary scan cell to analog test buses in said circuit; and
logic circuitry, responsive to a cell mode signal, having a parametric test mode in which said single-bit shift register element controls said analog switches.
2. A boundary scan cell as defined in claim 1, said logic circuitry being responsive to a combination of said cell mode signal and an analog mode signal.
3. A boundary scan cell as defined in claim 2, further including a second update latch for maintaining the logic state of control signal of said analog switches.
4. A boundary scan cell as defined in claim 2, said logic circuitry including a first gate for generating a parametric mode signal having the logic value of said combination of said cell mode signal and an analog mode signal; and a second gate responsive to said parametric mode signal and said bit value for generating an analog switch control signal.
5. A boundary scan cell as defined in claim 4, further including:
a first selector responsive to said parametric mode signal for connecting one of a cell output and said analog switch control signal to an input of said shift register element; and
a second selector responsive to said parametric mode signal for connecting one of the output of said shift register element and the output of said update latch to the input of said update latch.
6. A boundary scan cell as defined in claim 5, wherein during said parametric test mode, said logic circuitry suppresses update of said associated pin logic state and enables update of an analog switch-control latch.
7. A boundary scan cell as defined in claim 5, wherein, during said parametric test mode, said logic circuitry enables said shift register element to control said analog switches while bits are shifting in said BSSR.
8. A boundary scan cell as defined in claim 5, said circuit further including a comparator having inputs connected to an analog bus that is connected to pins under test and another bus, said comparator having an output connected to a test data output.
9. A boundary scan cell as defined in claim 8, said circuit further including a selector for selecting between said serial test data output and said comparator output under control of said parametric mode signal.
10. A boundary scan cell as defined in claim 1, wherein during said parametric test mode, said logic circuitry suppresses update of said associated pin logic state and enables update of an analog switch-control latch.
11. A boundary scan cell as defined in claim 1, wherein during said parametric test mode, said logic circuitry enables said shift register element to control said analog switches while bits are shifting in said BSSR.
12. A boundary scan cell as defined in claim 1, wherein, for a pair of scan cells associated with a differential pin pair, said logic circuitry in said pair of scan cells being interconnected so that one of said analog switches of each scan cell of said pair of scan cells is controlled by said parametric mode signal and a combination of the bit values of said scan cells, and the other analog switch of each scan cell of said pair of scan cells is controlled by a combination of said parametric mode signal and only the bit value of its associated scan cell.
13. A boundary scan cell as defined in claim 12, each of said associated cells further including a second update latch for storing said bit value, said combination including the logic state of said second update latch.
14. A boundary scan cell as defined in claim 1, said circuit further including a comparator whose compared inputs are connected to an analog bus that is connected to pins under test and another bus, said comparator having an output connected to a circuit test data output.
15. A boundary scan cell as defined in claim 14, said circuit further including a selector for selecting between said circuit test data output and said comparator output under control of a parametric mode signal.
16. A boundary scan cell as defined in claim 1, said boundary scan cell being an IEEE 1149.1-compliant boundary scan cell associated with a digital pin.
17. An analog boundary module (ABM) containing boundary scan cells as defined in claim 1, said ABM being compliant with IEEE 1149.4.
18. An ABM as defined in claim 17, said logic circuitry of each of said boundary scan cells having an output connected to a clock input of a cell update latch and having logic gates that prevent updating of the state of said associated pin and enable updating of analog switch control signals during said parametric test mode.
19. An ABM as defined in claim 17, said logic circuitry of each of said boundary scan cells having an output connected to a clock input of an analog switch update latch and having logic gates that enable, during said parametric test mode, updating of said analog switch update latch during a test access port controller shift state.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A connection method for establishing connection between a first station and a second station in a wireless network using different frame formats, the first station supporting both a first frame format and a second frame format, the second station supporting only the first frame format, the method comprising the steps of:
causing the first station to be a parent station for using two channels; and
transmitting, from the first station to the second station, data in the first frame format over one channel and transmitting data in the second frame format over the other channel so as to establish a connection with the second station.
2. A connection method for establishing connection between a first station and a second station in a wireless network using different frame formats, the first station supporting both a first frame format and a second frame format, the second station supporting only the first frame format, the method comprising the steps of:
causing the first station to be a parent station; and
transmitting, from the first station to the second station, data in the second frame format for a predetermined time period and thereafter transmitting data in the first frame format so as to establish a connection with the second station.
3. A connection method for establishing connection between a first station and a second station in a wireless network using different frame formats, the first station supporting both a first frame format and a second frame format, the second station supporting only the first frame format, the method comprising the steps of:
causing the first station to be a parent station;
transmitting, from the first station to the second station, data in the first frame format for a predetermined time period;
if the connection is unsuccessful, causing the first station to relinquish its role as the parent station so as to change to a listening mode;
causing the second station to be a parent station; and
transmitting, from the second station to the first station, data in the second frame format so as to establish a connection with the first station.
4. A connection method according to claim 1 wherein the frame formats are of different lengths and wherein the first frame format is a short frame format and the second frame format is a long frame format.
5. A connection method according to claim 2 wherein the different frame formats have different lengths and wherein the first frame format is a long frame format and the second frame format is a short frame format.
6. A connection method according to claim 3 wherein the different frame formats have different lengths and wherein the firs frame format is a short frame format and the second frame format is a long frame format.
7. A wireless network comprising a first station configured to support both a first frame format and a second frame format and a second station configured to support only one of said long or short frame formats the first station being further configured to be a parent station having two data channels such that the first station can transmit to the second station data in the first frame format over one channel and data in the second frame format over the other data channel so as to establish a connection with the second station.
8. A wireless network according to claim 7 wherein the first and second stations comprise PCs.
9. A wireless network according to claim 8 wherein the first frame format is a long frame format and the second frame format is a short frame format.