1. A tunable, multi-band filter comprising:
a tank circuit that includes at least two parallel branches, wherein a first branch of said at least two parallel branches includes a switching transistor and a second branch of said at least two parallel branches includes a fixed inductor, wherein said gate terminal of said switching transistor is coupled to receive a control voltage VC to tune said filter between multiple different filter responses; and
an inverter to invert said control voltage VC and apply said inverted signal to a source terminal of said switching transistor to improve the linearity of said filter;
wherein said tank circuit and said inverter are integrated on a semiconductor chip.
2. The tunable, multi-band filter of claim 1, further comprising:
a second tank circuit that includes at least two parallel branches, wherein a first branch of said at least two parallel branches of said second tank circuit includes a second switching transistor and a second branch of said at least two parallel branches of said second tank circuit includes a fixed inductor, wherein said gate terminal of said second switching transistor is coupled to receive said control voltage VC to tune said filter between multiple different responses and said inverter applies said inverted signal to a source terminal of said second switching transistor to improve the linearity of said filter; and
at least one series reactive element coupling said first and second tank circuits.
3. The tunable, multi-band filter of claim 1, wherein:
said first branch of said tank circuit further includes a first capacitor coupled to a drain terminal of said switching transistor and a second capacitor coupled to a source terminal of said switching transistor.
4. The tunable, multi-band filter of claim 1, wherein:
said switching transistor includes a parasitic off capacitance when it is in the off state that is used as a reactive element within the filter to achieve a desired filter response when the switching transistor is in the off state.
5. The tunable, multi-band filter of claim 1, wherein:
said semiconductor chip is a front end module.
6. The tunable, multi-band filter of claim 1, wherein:
said semiconductor chip is a dedicated filter chip.
7. A system comprising:
at least one dipole antenna; and
a semiconductor chip coupled to said at least one dipole antenna, said semiconductor chip having a tunable, multi-band filter integrated thereon, said tunable, multi-band filter comprising:
a switching transistor having a gate terminal that is coupled to receive a control voltage VC to tune said tunable, multi-band filter between multiple different responses; and
an inverter to invert said control voltage VC and apply said inverted signal to a source terminal of said switching transistor to improve the linearity of said filter.
8. The system of claim 7, wherein:
said front end module chip further includes first radio circuitry operative within a first frequency band and second radio circuitry operative within a second frequency band, wherein both said first radio circuitry and said second radio circuitry are coupled to said tunable, multi-band filter.
9. The system of claim 7, further comprising:
a controller to cause control signals to be delivered to said tunable, multi-band filter to change a filter response thereof.
10. The system of claim 7, wherein:
said switching transistor is within a first branch of a first tank circuit of said tunable, multi-band filter, said first tank circuit also including a second branch having a fixed inductor; and
said tunable, multi-band filter further includes:
a second tank circuit having at least a first and second branch, said first branch of said second tank circuit having a second switching transistor and said second branch of said second tank circuit having a fixed inductor, said second switching transistor having a gate terminal that is coupled to receive said control voltage VC and a source terminal that is coupled to receive said inverted signal from said inverter; and
at least one series reactive element coupling said first and second tank circuits.
11. The system of claim 10, wherein:
said first branch of said tank circuit further includes a first capacitor coupled to a drain terminal of said switching transistor and a second capacitor coupled to a source terminal of said switching transistor.
12. The system of claim 7, wherein:
said switching transistor includes a parasitic off capacitance when it is in the off state, wherein said parasitic off capacitance of said switching transistor is used as a reactive element within the filter to achieve a desired filter response when the switching transistor is in the off state.
13. The system of claim 7, wherein:
said semiconductor chip is a front end module.
14. The system of claim 7, wherein:
said semiconductor chip is a dedicated filter chip.
15. A method comprising:
providing a control voltage signal to a gate terminal of a first switching transistor within a tunable, multi-band filter to change said filter between multiple different filter responses; and
providing an inverted version of said control voltage signal to a source terminal of said first switching transistor to improve the linearity of said tunable, multi-band filter.
16. The method of claim 15, further comprising:
providing said control voltage signal to a gate terminal of a second switching transistor within said tunable, multi-band filter, at the same time that said control voltage signal is provided to said gate terminal of a first switching transistor, to change said filter between multiple different filter responses; and
providing said inverted version of said control voltage signal to a source terminal of said second switching transistor, at the same time that said inverted version of said control voltage signal is provided to said source terminal of a first switching transistor, to improve the linearity of said tunable, multi-band filter.
17. The method of claim 15, wherein:
said first switching transistor is within a first branch of a first tank circuit of said tunable, multi-band filter, said first tank circuit also including a second branch having a fixed inductor.
18. The method of claim 17, wherein:
said first branch of said tank circuit further includes a first capacitor coupled to a drain terminal of said first switching transistor and a second capacitor coupled to a source terminal of said first switching transistor.
19. The method of claim 17, wherein:
said first switching transistor includes a parasitic off capacitance when it is in the off state, wherein said parasitic off capacitance of said switching transistor is used as a reactive element within the tunable, multi-band filter to achieve a desired filter response when the switching transistor is in the off state.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A driving method of driving a photoelectric conversion device, the photoelectric conversion device including: a pixel array in which a plurality of pixels are arrayed in a matrix; a plurality of vertical signal lines each provided to a corresponding column of the matrix; a plurality of amplifiers each electrically connected to a corresponding one of the plurality of vertical signal lines; and a plurality of isolation switches each provided between a corresponding one of the plurality of vertical signal lines and a corresponding one of the plurality of amplifiers, wherein each pixel includes a photodiode, a floating diffusion, a transfer switch which transfers a charge of the photodiode to the floating diffusion, and an amplification transistor, and each pixel outputs a signal to the vertical signal line in accordance with a potential of the floating diffusion, and wherein each amplifier includes a differential amplifier, a clamp capacitor arranged between the isolation switch and an input terminal of the differential amplifier, and a reset switch interposed between the input terminal and an output terminal of the differential amplifier, the method comprising, in a period for reading out signals from pixels of a row:
turning off the reset switches before turning on the transfer switches;
turning on the transfer switches while the reset switches are kept in a turned-off state; and
keeping the isolation switches in a turned-off state at least in a period when a transfer pulse for controlling the transfer switches transits.
2. The method according to claim 1, wherein each of the plurality of isolation switches includes an NMOS transistor.
3. The method according to claim 1, wherein each of the plurality of isolation switches includes an NMOS transistor and a PMOS transistor, which are connected in parallel and are driven by signals having opposite logic levels such that the NMOS transistor and the PMOS transistor are turned off at least in the period when the transfer pulse for controlling the transfer switch transits.
4. The method according to claim 3, wherein the NMOS transistor and the PMOS transistor have a same size.
5. The method according to claim 3, wherein one diffusion region of the NMOS transistor is connected to one diffusion region of the PMOS transistor, and another diffusion region of the NMOS transistor is connected to another diffusion region of the PMOS transistor.
6. The method according to claim 1,
wherein each of the plurality of isolation switches includes:
a first NMOS transistor connected between the vertical signal line and the input terminal of the differential amplifier,
a first PMOS transistor connected between the vertical signal line and the input terminal of the differential amplifier, and
a second NMOS transistor and a second PMOS transistor respectively having a source and a drain connected to the input terminal of the differential amplifier,
wherein the first NMOS transistor and the second PMOS transistor are driven by an isolation signal, and
wherein the first PMOS transistor and the second NMOS transistor are driven by an inverted isolation signal serving as an inverted signal of the isolation signal.
7. The method according to claim 6, wherein an ON resistance of the first NMOS transistor is equal to an ON resistance of the first PMOS transistor.
8. The method according to claim 7, wherein a parasitic capacitance between a node to which the isolation signal is supplied and the input terminal is equal to a parasitic capacitance between a node to which the inverted isolation signal is supplied and the input terminal.
9. The method according to claim 1, wherein a gain of each of the differential amplifiers is variable.
10. The method according to claim 1, wherein the photoelectric conversion device is incorporated in an imaging device that includes a processing circuit, which processes a signal supplied from the photoelectric conversion device.