1-7. (canceled)
8. A method for manufacturing a solar cell, comprising:
(a) preparing a silicon semiconductor substrate doped with a first conductive impurity;
(b) forming an emitter layer on the substrate by doping an upper portion of the substrate with a second conductive impurity having the opposite polarity to the first conductive impurity;
(c) forming an etching mask pattern at a front electrode connection area on the emitter layer using a paste comprising inorganic powder having a tap density of 0.01 to 20 gcm3, an organic solvent and a binder;
(d) etching back the emitter layer by using the etching mask pattern as a mask;
(e) removing the etching mask pattern remaining after the etch-back;
(f) forming an anti-reflection film over a front surface of the substrate;
(g) establishing a connection between a front electrode and the front electrode connection area by penetrating through the anti-reflection film; and
(h) establishing a connection between a rear electrode and a rear surface of the substrate.
9. The method for manufacturing a solar cell according to claim 8, wherein the binder includes an organic solvent and a binder resin.
10. The method for manufacturing a solar cell according to claim 8,
wherein the first conductive impurity is a p-type impurity and the second conductive impurity is an n-type impurity.
11. The method for manufacturing a solar cell according to claim 8,
wherein the inorganic powder includes metal or metal oxide powder, or mixtures thereof.
12. The method for manufacturing a solar cell according to claim 8,
wherein the inorganic powder of step (c) includes any one metal or metal oxide powder selected from the group consisting of Si, Ti, ITO, SiO2, TiO2, Bi2O3 and PbO, or mixtures thereof.
13. The method for manufacturing a solar cell according to claim 8,
wherein the inorganic powder has an average particle diameter of 1 nm to 10 \u03bcm.
14. The method for manufacturing a solar cell according to claim 8,
wherein the inorganic powder has an average particle diameter of 10 nm to 5 \u03bcm.
15. The method for manufacturing a solar cell according to claim 8,
wherein the inorganic powder is coated with silane compound, silicon oil or fatty acid.
16. The method for manufacturing a solar cell according to claim 8,
wherein, in the step (d), the emitter layer is etched back using a selective wet etchant in which HNO3, HF, CH3COOH and H2O are mixed at a volume ratio of 10:0.1\u02dc0.01:1\u02dc3:5\u02dc10.
17. The method for manufacturing a solar cell according to claim 16,
wherein the selective wet etchant has an etch rate of 0.08 to 0.12 \u03bcmsec for an area doped with a high concentration of impurity in the emitter layer and an etch rate of 0.01 to 0.03 \u03bcmsec for an area doped with a low concentration of impurity in the emitter layer.
18. The method for manufacturing a solar cell according to claim 8,
wherein, in the step (d), the emitter layer is etched back using an alkaline wet etchant or a plasma dry etchant.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A system to control operation of an insulated gate bipolar transistor, the system comprising:
a detector for detecting a fault state of an insulated gate bipolar transistor (IGBT), the detector including a circuit responsive to an induced voltage across a stray inductance; and
a controller including a first stage and a second stage for controlling and shutting off the IGBT responsive to detection of a fault state, the first stage comprising a negative feedback control unit that is coupled to the induced voltage across the stray inductance and that dynamically controls a rate of change in a fault current based in part on the fault state of the IGBT of the circuit, wherein the induced voltage across the stray inductance is between a Kelvin emitter and a power emitter of the insulated gate bipolar transistor.
2. The system of claim 1, wherein the first stage controls a rate of change in a fault current for a first interval, and the second stage turns off the IGBT upon expiration of the first interval.
3. The system of claim 1 wherein the detector includes a circuit responsive to a magnitude and a duration of a change in current with respect to time.
4. The system of claim 1 wherein the first stage dynamically controls a rate of change in a fault current based at least in part on the fault state of a circuit and the second stage turns OFF the IGBT at a slower rate than a conventional rate.
5. The system as recited in claim 4, wherein the rate of change in the fault current is substantially linear.
6. The system of claim 1, wherein the negative feedback control unit is coupled to a resistor capacitor (RC) network across the stray inductance.
7. The system of claim 6, wherein the negative feedback control unit dynamically controls a rate of change in the fault current by operating a transistor in a linear range.
8. A method to control operation of Insulated Gate Bipolar transistor (IGBT), the method including the steps of:
detecting a fault state of a transistor with a circuit responsive to an induced voltage across a stray inductance;
dynamically controlling a rate of change in a fault current based at least in part on the fault state for a first interval; and
turning off the IGBT at a desired rate upon expiration of the first interval, wherein the step of detecting the fault state includes detecting the induced voltage across the stray inductance between a Kelvin emitter and a power emitter of the IGBT.
9. The method of claim 8 wherein detecting a fault state of the IGBT includes detecting a magnitude and a duration of a change in current with respect to time.
10. The method of claim 8 wherein dynamically controlling a rate of change in a fault current based at least in part on the fault state includes reducing the fault current to a defined level.
11. The method of claim 8, wherein the rate of change in a fault current is controlled to provide a linear reduction in fault current to a defined level.
12. The system of claim 8 wherein dynamically controlling a rate of change in a fault current based at least in part on the fault state further includes turning OFF the transistor at a slower rate than a conventional rate.