1. A device for the encoding of information symbols to transmit or to record, and the correcting errors among the symbols received or read, according to codes defined over a Galois field Fq, where q is an integer greater than 2 and equal to a power of a prime number, and in which a set of elements of Fq are considered which are denoted yl(j), where j=1, . . . ,R with 1\u2266R\u2266q\u22121 and l=0, . . . ,p\u22121 with p>1, said device comprising:
a Reed-Solomon encoder;
a Reed-Solomon decoder; and
a unit serving to calculate the inverse of a Vandermonde matrix;
registers A in which there are stored
for the encoding, said information symbols, and
for the error correction, the symbols received or read after they have been corrected;
registers S in which there are stored
for the encoding, the symbols output from said Reed-Solomon encoder, and
for the correction of errors, the symbols input to said Reed-Solomon decoder; and
registers Y in which said quantities yl(j) are stored.
2. A The device according to claim 1, in which said Reed-Solomon decoder is of length (q\u22121), and further comprising a conversion-X table placing the indices of any register of length R opposite the respective elements of the Galois field Fq.
3. The device according to claim 1 or claim 2, charaer in that which in said registers the powers yl(j)s of the symbols yl(j), where s=2, . . . ,p\u22121, are also stored.
4. The device according to claim 1 or claim 2, further comprising multiplier circuits calculating the powers yl(j)s of the symbols yl(j), where s=2, . . . ,p\u22121, after the values of those symbols have been read in the registers during the post-processing steps.
5. A The device according to claim 1 or claim 2, further comprising a state machines adapted to organize activation and deactivation of all the signals driving the encoding and error correcting operations.
6. The device according to claim 1 or claim 2, further comprising a control unit in the form of an Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA)
7. A The device according to claim 1 or claim 2, further comprising a control unit in the form of a data processing device capable of being controlled by a computer program.
8. A computer program, containing instructions adapted to operate said control unit of said device according to claim 7.
9. An apparatus for sending and receiving encoded digital signals, comprising means for modulating the encoded digital signals, a modulated data transmitter, a modulated data receiver, means for demodulating the encoded digital signals, means for calculating estimated information symbols from corrected received words, and a device according to claim 1 or claim 2.
10. An apparatus for recording and reading encoded digital signals, comprising means for modulating the encoded digital signals, a modulated data recorder, a modulated data reader, means for demodulating the encoded digital signals, means for calculating estimated information symbols from corrected read words, and a device according to claim 1 or claim 2.
11. A device for encoding information symbols into a linear code, and for detecting error locations and magnitudes of encoded information symbols of the linear code, comprising:
a Reed-Solomon encoder, adapted to encode information symbols into a Reed-Solomon codes;
a Reed-Solomon decoder, adapted to decode Reed-Solomon code; and
address conversion means for matching locations of the linear code to locations of the Reed-Solomon code.
12. The device according to claim 11, further comprising:
pre-processing means for processing information symbols to be input to said Reed-Solomon encoder and encoded information symbols to be input to said Reed-Solomon decoder;
post-processing means for processing symbols output from said Reed-Solomon decoder or from said Reed-Solomon encoder; and
a command unit. adapted to organize activation and deactivation of signals driving the encoding, the decoding, the pre-processing and the post-processing operations.
13. The device according to claim 11, further comprising:
a first register, adapted to store the information symbols or encoded information symbols;
a second register, adapted to store the symbols output from said Reed-Solomon encoder or the symbols input to said Reed-Solomon decoder; and
a third register, adapted to store predetermined values of the first linear code.
14. The device according to claim 12, wherein said post-processing means comprises a unit for calculating an inverse of a Vandermonde matrix.
15. The device according to any one of claims 11 to 14, wherein the linear code is an algebraic geometric code.
16. A device for encoding information symbols into a liner code, comprising:
pre-processing means for performing first operations on information symbols to be encoded and predetermined values of the linear code;
a Reed-Solomon encoder adapted to encode the pre-processed information symbols into a Reed-Solomon code and outputting encoded information symbols; and
post-processing means for performing second operations on the information symbols to be encoded, the symbols encoded by said Reed-Solomon encoder and the predetermined values of the linear code.
17. The device according to claim 16, further comprising:
a plurality of first registers each for storing the information symbols to be encoded;
a plurality of second registers each for storing information symbols encoded by said Reed-Solomon encoder; and
a plurality of third registers each for storing the predetermined values of the linear code.
18. The device according to claim 16, wherein said post-processing means comprises means for calculating an inverse of a Vandermonde matrix from values stored in the plurality of third registers.
19. The device according to claim 16, wherein the linear code is an algebraic geometric code.
20. A device for decoding encoded information symbols of a linear code, comprising:
pre-processing means for performing first operations on encoded information symbols to be decoded and predetermined values of the linear code;
a Reed-Solomon decoder, adapted to decode the pre-processed information symbols; and
post-processing means for performing second operations on the encoded information symbols to be decoded, the symbols decoded by said Reed-Solomon decoder, and the predetermined values of the linear code.
21. The device according to claim 20, further comprising:
a plurality of first registers each for storing encoded information symbols to be decoded;
a plurality of second registers each for storing decoded information symbols; and
a plurality of third registers each for storing predetermined values of the linear code.
22. The device according to claim 20, wherein said post-processing means comprises means for calculating an inverse of a Vandermonde matrix from values stored in sad the plurality of third registers.
23. The device according to claim 20, wherein the linear code is an algebraic geometric code.
24. A method for encoding information symbols into a linear code, comprising the steps of:
pre-processing the information symbols by performing first operations on the information symbols to be encoded and predetermined values of the linear code;
encoding the pre-processed information symbols into a Reed-Solomon code; and
post-processing the encoded information symbols by performing second operations on the information symbols to be encoded, the encoded information symbols. and the predetermined values of the linear code.
25. A method for decoding encoded information symbols of a linear code, comprising the steps of:
pre-processing the encoded information symbols by performing first operations on the encoded information symbols to be decoded and predetermined values of the linear code;
decoding the pre-processed symbols as a Reed-Solomon code; and
post-processing the decoded information symbols by performing second operations on the information symbols to be decoded, the decoded information symbols, and the predetermined values of the linear code.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An apparatus, comprising:
a memory configured to receive a calibration command and an attribute, comprising:
a first register configured to store a tuning data pattern; and
a second register configured to receive and store a tuning data pattern responsive, at least in part, to the memory receiving a calibration command;
wherein the memory is further configured to execute an operation on at least one of the tuning data pattern stored in the first register or the tuning data pattern stored in the second register based, at least in part, on the attribute.
2. The apparatus of claim 1, wherein the calibration command and attribute are received by the memory over a plurality of IO lines.
3. The apparatus of claim 1, further comprising:
a device coupled to the memory and configured to provide the calibration command and the attribute, the device further configured to provide a clock signal;
wherein the memory is configured to receive the clock signal, the memory further configured to execute the operation based, at least in part, on the clock signal.
4. The apparatus of claim 3, wherein the device is further configured to vary a frequency of the clock signal.
5. The apparatus of claim 1, wherein the first register comprises non-volatile memory and the second register comprises volatile memory.
6. The apparatus of claim 1, wherein the operation comprises a read volatile operation and wherein the memory is configured to provide the tuning data pattern stored in the second register after a plurality of dummy cycles have elapsed after receipt of the attribute.
7. The apparatus of claim 1, wherein the attribute corresponds to a multi-input operation.
8. The apparatus of claim 1, wherein the attribute is a non-volatile programming attribute, volatile refresh attribute, non-volatile erase attribute, read volatile attribute, or volatile program attribute.
9. The apparatus of claim 1, wherein the tuning data pattern stored in the first register is based, at least in part, on silicon processes, PCB loads, voltage variations, temperature fluctuations, or any combination thereof.
10. The apparatus of claim 1, wherein the second register is further configured to receive a plurality of tuning data patterns responsive at least in part, to the memory receiving the calibration command.
11. An apparatus, comprising:
a memory configured to receive a read command, the memory further configured to provide a tuning data pattern responsive, at least in part, to receipt of the read command and to provide the tuning data pattern after a plurality of dummy cycles have elapsed after receipt of the read command.
12. The apparatus of claim 11, wherein the memory is further configured to operate in accordance with the SPI protocol.
13. The apparatus of claim 11, wherein the memory is further configured to provide the tuning data pattern based, at least in part, on a short calibration flag.
14. The apparatus of claim 11, wherein the memory is further configured to provide data corresponding to the read command after providing the tuning data pattern.
15. The apparatus of claim 11, further comprising a bus having a plurality of IO lines and wherein the read command is provided over the plurality of IO lines.
16. The apparatus of claim 11, wherein the memory is configured to provide as plurality of tuning data patterns on a plurality of IO lines, wherein at least one of the tuning data patterns being different than another one of the tuning data patterns.
17. A method, comprising:
providing a tuning data pattern at a first frequency responsive, at least in part, to receipt of a clock signal having a first frequency; and
providing the tuning data pattern at a second frequency responsive, at least in part, to receipt of a clock signal having a second frequency.
18. The method of claim 17, wherein providing the tuning data pattern comprises providing the tuning data pattern responsive, at least in part, to receipt of a calibration command and an attribute.
19. The method of claim 17, further comprising:
comparing the tuning data pattern provided at the first frequency and the tuning data pattern provided at the second frequency.
20. The method of claim 19, wherein providing the tuning data patterns comprises providing the tuning data patterns from a memory coupled to a device, the method further comprising:
determining a sample point based, at least in part, on said comparing the tuning data pattern provided at the first frequency and the tuning data pattern provided at the second frequency at the device.
21. The method of claim 17, wherein said providing a tuning data pattern at a first:
frequency comprises providing the tuning data pattern from a memory over a plurality of IO lines.
22. The method of claim 17, wherein providing the tuning data pattern comprises providing the tuning data pattern responsive, at least in part, to receipt of a read volatile attribute.
23. The method of claim 17, wherein the second frequency is greater than the first frequency.
24. A method, comprising:
receiving at a memory a read command;
providing a tuning data pattern responsive, at least in part, to receipt of the read command; and
after providing the tuning data pattern from the memory, providing read data corresponding to the read command.
25. The method of claim 24, further comprising:
before said providing a tuning data pattern, waiting for a plurality of dummy cycles to elapse after receipt of the read command.
26. The method of claim 24, wherein said providing from the memory a tuning data pattern comprises:
determining the status of a short calibration flag; and
if it is determined that the short calibration flag has an enabled state, providing the a tuning data pattern.
27. The method of claim 24, wherein said providing from the memory a tuning data pattern comprises:
providing the tuning data pattern from a non-volatile memory to a volatile memory; and
providing the tuning data pattern from the volatile memory.
28. A method, comprising:
receiving a calibration command;
providing a tuning data pattern from a first register to a second register responsive, at least in part, to receipt of the calibration command;
receiving an attribute; and
executing an operation on the tuning data pattern based, at least in part, on the attribute.
29. The method of claim 28, wherein the tuning data pattern is a first data tuning pattern, the method further comprising:
after said receiving the attribute, receiving a second tuning data pattern.
30. The method of claim 29, wherein receiving a second tuning data pattern comprises storing the second tuning data pattern in the first register, and wherein the method further comprises providing the second tuning data pattern from the first register to the second register.
31. The method of claim 28, further comprising:
after said receiving the attribute, waiting for a plurality of dummy cycles to elapse.
32. The method of claim 28, wherein said executing an operation comprises:
providing the tuning data pattern from the second register to a bus.