1. A control circuit for controlling the operation of a switching converter to provide a regulated load current to a load, the switching converter comprising an inductor and a high-side and a low side-transistor for switching the load current flowing through the inductor, the circuit comprising:
a digital modulator configured to provide a modulated signal having a duty cycle determined by a digital duty cycle value;
a current sense circuit to be coupled to at least one of the high side and low side transistors and configured to regularly sample a load current value;
a comparator, coupled to the current sense circuit and configured to compare the sampled load current value with a first threshold and to provide a respective comparator output signal, the first threshold being dependent on a defined desired output current and the comparator output signal being indicative of whether the sampled current value is less than or greater than the desired output current; and
a regulator configured to receive the comparator output signal (VCOMP) and to calculate an updated digital duty cycle value.
2. The control circuit of claim 1, wherein the comparator is configured to compare the sampled load current value with the first threshold and a second and a third threshold such that the comparator output signal is indicative of whether the sampled load current differs from the desired output current by more than an amount determined by the second and third threshold, respectively.
3. The control circuit of claim 2, wherein the comparator output value is set to a first value, when the sampled load current is below the second threshold, to a second value when the sampled load current is between the second threshold and the first threshold, to a third value when the sampled load current is between the first threshold and the third threshold, and to a fourth value when the sampled load current is higher than the third threshold.
4. The control circuit of claim 3, wherein the first, second third, and fourth values nonlinearly depend on the sampled input current value.
5. The control circuit of claim 1 wherein the regulator has a integrating path and a proportional path, both paths including a gain and the proportional path including a saturation element.
6. The control circuit of claim 1 wherein the comparator output signal represents a nonlinear quantization of the load current, the quantization being that coarse that the regulated load current performs a limit cycle across the desired load current value with a frequency corresponding to the modulation frequency of the modulator.
7. The control circuit of claim 1 wherein
the digital modulator is configured to set the modulated signal to such a value that the load current flow is stopped in response to a dim control signal, and
wherein the regulator is configured to maintain the digital duty cycle value while the dim signal stops the load current flow.
8. The control circuit of claim 7, wherein the dim signal is a modulated signal with a modulation period being longer by a factor of at least 10 than a modulation period of the digital modulator.
9. The control circuit of claim 1, wherein the current sense circuit includes a first sense transistor arrangement including a sense transistor to be coupled to the high-side transistor or the low-side transistor and a current source configured to set the sense transistor current to a defined value representing a comparator threshold.
10. The control circuit of claim 9, wherein a control electrode of the sense transistor and a control electrode of the corresponding high-side or low-side transistor are connected to have the same potential, and wherein
the comparator is configured to compare the potentials sourcedrain electrodes of the sense transistor and the corresponding high-side or low-side transistor.
11. A method for controlling the operation of a switching converter to provide a regulated load current to a load, the switching converter comprising an inductor and a high-side and a low side-transistor for switching the load current flowing through the inductor; the method comprising:
providing a modulated signal that has a duty cycle determined by a digital duty cycle value;
regularly sampling a load current value;
comparing the sampled load current value with a first threshold to provide a respective comparison output signal, wherein the first threshold is dependent on a defined desired output current and the comparison output signal is indicative of whether the sampled current value is lower or higher than the desired output current; and
calculating an updated digital duty cycle value from the comparison output current in accordance with a given control law.
12. The method of claim 11, wherein the comparing the sampled load current value with a first threshold comprises:
providing, the comparison output signal and a predefined output value that depends on a state of a state machine; and
comparing the sampled load current value with a variable threshold that depends on the state of the state machine;
wherein each state of the state machine is associated with a defined output value and a defined threshold; and
wherein the number of defined output values equals the number of defined thresholds plus one.
13. The method of claim 11, wherein sampling a load current value comprises sampling a source or drain potential of the high-side or low-side transistor.
14. The method of claim 13, wherein comparing the sampled load current value with a first threshold comprises comparing the source or drain potential of the high-side or low-side transistor with a respective source or drain potential of a corresponding sense transistor,
wherein the drain or source current of the sense transistor is set to a value representing the first threshold.
15. The method of claim 11 wherein sampling a load current value comprises sampling a load current value at the low-side transistor or at the high-side transistor, dependent on the digital duty cycle value.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An image sensor integrated circuit, comprising:
a plurality of photodetectors generating electrons excited by incident photons, each of the plurality of photodetectors including:
an n-type region receiving the electrons excited by the energy of the photons;
a plurality of nodes, wherein each of the plurality of photodetectors has a corresponding node of the plurality of nodes;
a plurality of transfer devices controlling a transfer of the electrons from said each of the plurality of photodetectors to the corresponding node, each of the plurality of transfer devices including:
a first terminal coupled to the n-type region of one of the plurality of photodetectors;
a second terminal coupled to one of the plurality of nodes; and
a control terminal receiving the control signal, wherein the transfer of the electrons occurs between the first terminal and the second terminal in response to a control signal of sufficient value applied to the control terminal;
a plurality of p-type regions having a concentration stronger than a background concentration, wherein each of the plurality of p-type regions has a lateral position at least partly under the control terminal of a transfer device of the plurality of transfer devices controlling the transfer of electrons from a photodetector of the plurality of photodetectors to the corresponding node of the photodetector, and each of the plurality of p-type regions has a lateral position at least partly under the corresponding node;
a plurality of reset devices, wherein each of the plurality of nodes has a corresponding reset device of the plurality of reset devices, and said each of the plurality of nodes is reset when the corresponding reset device is active;
row and column circuitry; and
a plurality of signal devices coupling the plurality of nodes to the row and column circuitry.
2. The circuit of claim 1, wherein at least part of each of the plurality of p-type regions is vertically positioned to block the electrons from traveling between the photodetector and the corresponding node below a region controlled by the control terminal of the transfer device.
3. The circuit of claim 1, wherein the n-type region includes:
a first n-type region receiving the electrons excited by the energy of the photons; and
a second n-type region adjacent to the first region, wherein a difference in n-type concentration between the first n-type region and the second n-type region causes electrons to move from the first n-type region to the second n-type region.
4. The circuit of claim 1, wherein the n-type region of the plurality of photodetectors is at a first range of depths, and the plurality of p-type regions is at a second range of depths includes a subrange of depths shallower than the first range of depths.
5. The circuit of claim 1, wherein the plurality of reset devices and the plurality of signal devices are positioned in a second plurality of p-type regions.
6. The circuit of claim 1, wherein the plurality of p-type regions has a first p-type doping concentration, and the plurality of reset devices comprises a second plurality of p-type regions having a second p-type doping concentration, and the second p-type doping concentration is greater than the first p-type doping concentration.
7. The circuit of claim 1, wherein the plurality of reset devices further comprises a second plurality of p-type regions, and each of the second plurality of p-type regions is positioned away from each of the plurality of p-type regions, to prevent merging of depletion regions.
8. The circuit of claim 1, wherein the plurality of reset devices further comprises a second plurality of p-type regions, and a separation distance between implantation areas of a neighboring one of the second plurality of p-type regions and a neighboring one of the first plurality of p-type regions is in a range of 0.3 to 0.6 microns.
9. The circuit of claim 1, wherein the plurality of reset devices further comprises a second plurality of p-type regions, and a separation distance between a neighboring one of the second plurality of p-type regions and a neighboring one of the first plurality of p-type regions is in a range of 0.3 to 0.6 microns.
10. The circuit of claim 1, wherein the plurality of reset devices further comprises a second plurality of p-type regions, and a p-type concentration of implanted dopants that diffused over a separation distance from an implantation area of a neighboring one of the second plurality of p-type regions up to a neighboring one of the first plurality of p-type regions is no more than 3.2 times greater than a background concentration of the p-type substrate.
11. The circuit of claim 1, wherein the plurality of reset devices further comprises a second plurality of p-type regions, and each of the second plurality of p-type regions has an implantation area overlapped by the control terminal of one or more of the plurality of transfer devices.
12. The circuit of claim 1, wherein the plurality of reset devices further comprises a second plurality of p-type regions, and each of the second plurality of p-type regions has an implantation area overlapped by 0.1 to 0.3 microns of the control terminal of one or more of the plurality of transfer devices.
13. The circuit of claim 1, wherein the plurality of reset devices further comprises a second plurality of p-type regions each formed by two boron implants.
14. The circuit of claim 1, wherein the plurality of reset devices further comprises a second plurality of p-type regions each formed by a first boron implant and a second boron implant, wherein the first boron implant has a first energy range of 40 to 60 keV and a first dose range of 1.5\xd71012 to 2.0\xd71012 atomscm2, and the second boron implant has a second energy range of 180 to 220 keV and a second dose range of 1.0\xd71012 atomscm2 to 1.4\xd71012 atomscm2.
15. The circuit of claim 1, further comprising:
a second plurality of p-type regions isolating neighboring photodetectors from each other.
16. The circuit of claim 1, wherein the plurality of p-type regions isolate neighboring photodetectors from each other.
17. The circuit of claim 1, wherein each of the plurality of transfer devices includes a body connecting the first terminal and the second terminal such that the control terminal controls the transfer of the electrons between the first terminal and the second terminal through the body, and a dielectric between the control terminal and the body, the dielectric satisfying a lifetime specification of the image sensor integrated circuit when the control signal is applied with the channel formel, the dielectric failing the lifetime specification of the image sensor integrated circuit if the control signal is applied with at least one of the first terminal and the second terminal at a ground voltage of the image sensor integrated circuit.
18. The circuit of claim 1, wherein the plurality of signal devices includes a plurality of row select transistors coupled to the row and column circuitry and a plurality of source follower transistors coupled to the plurality of nodes.
19. The circuit of claim 1, wherein the plurality of photodetectors is a plurality of photodiodes.
20. The circuit of claim 1, wherein each measurement of the total of the photons is corrected by correlated multiple sampling with a prior measurement of the total of the photons.
21. A method of fabricating an image sensor integrated circuit having a plurality of photodetectors using energy of photons reaching the plurality of photodetectors to excite electrons; a plurality of nodes, each of the plurality of photodetectors having a corresponding node of the plurality of nodes; a plurality of transfer devices each with a first terminal coupled to one of the plurality of photodetectors, a second terminal coupled to the corresponding node, and a control terminal causing a transfer of the electrons from the first terminal to the second terminal in response to receiving a control signal of sufficient value; a plurality of reset devices, each of the plurality of nodes having a corresponding reset device of the plurality of reset devices, and said each of the plurality of nodes is reset when the corresponding reset device is active; and a plurality of signal devices coupling the plurality of nodes to row and column circuitry; the method comprising:
implanting a plurality of p-type regions having a concentration stronger than a background concentration;
implanting an n-type region for each of the plurality of photodetectors, the n-type region receiving the electrons excited by the energy of the photon;
depositing the control terminal for each of the plurality of transfer devices, each at least partly over a p-type region of the plurality of p-type regions, such that the transfer of electrons from a photodetector of the plurality of photodetectors to the corresponding node of the photodetector below a region controlled by the control terminal is blocked by a p-type region of the plurality of p-type regions;
implanting the plurality of nodes, wherein each of the plurality of photodetectors has the corresponding node of the plurality of nodes where the electrons are measured prior to removal, and the corresponding node is at least partly over the p-type region blocking the transfer of electrons from the photodetector to the corresponding node; and
implanting at least one n+ terminal for each of the plurality of transfer devices,
wherein said method forms row and column circuitry on the image sensor integrated circuit accessing the plurality of nodes.
22. The method of claim 21, further comprising:
implanting a second plurality of p-type regions isolating neighboring photodetectors from each other.
23. The method of claim 21, wherein the plurality of p-type regions isolate neighboring photodetectors from each other.
24. The method of claim 21, further comprising:
implanting a second plurality of p-type regions in which the plurality of reset devices, and the plurality of signal devices are formed.
25. The method of claim 21, wherein said depositing the control terminal for the plurality of transfer devices includes depositing the control terminal for the plurality of reset devices and the plurality of signal devices.
26. The method of claim 21, wherein said implanting at least one n+ terminal includes implanting the n+ terminals of the plurality of signal devices, and the plurality of reset devices.
27. The method of claim 21, wherein implanting the n-type region includes:
implanting a first n-type region receiving the electrons excited by the energy of the photons; and
implanting a second n-type region adjacent to the first region, wherein a difference in n-type concentration between the first n-type region and the second n-type region causes electrons to move from the first n-type region to the second n-type region.
28. The method of claim 21, wherein the n-type region of the plurality of photodetectors is at a first range of depths, and the plurality of p-type regions is at a second range of depths includes a subrange of depths shallower than the first range of depths.
29. The method of claim 21, further comprising:
implanting a second plurality of p-type regions in which the plurality of reset devices, and the plurality of signal devices are formed, the plurality of p-type regions having a first p-type concentration less than a second p-type concentration of the second plurality of p-type regions.
30. The method of claim 21, further comprising:
implanting a second plurality of p-type regions in which the plurality of reset devices is formed, and each of the second plurality of p-type regions is positioned away from each of the second plurality of p-type regions, to prevent merging of depletion regions of the first and second pluralities of p-type regions.
31. The method of claim 21, further comprising:
implanting a second plurality of p-type regions in which the plurality of reset devices is formed, and a separation distance between implantation areas of a neighboring one of the second plurality of p-type regions and a neighboring one of the plurality of p-type regions is in a range of 0.3 to 0.6 microns.
32. The method of claim 21, further comprising:
implanting a second plurality of p-type regions in which the plurality of reset devices is formed, and a p-type concentration of implanted dopants that diffused over a separation distance from an implantation area of a neighboring one of the second plurality of p-type regions up to a neighboring one of the plurality of p-type regions is no more than 3.2 times greater than a background concentration of a p-type substrate.
33. The method of claim 21, further comprising:
implanting a second plurality of p-type regions in which the plurality of reset devices is formed, and each of the second plurality of p-type regions has an implantation area overlapped by the control terminal of one or more of the plurality of transfer devices.
34. The method of claim 21, further comprising:
implanting a second plurality of p-type regions in which the plurality of reset devices is formed, and each of the second plurality of p-type regions has an implantation area overlapped by 0.1 to 0.3 microns of the control terminal of one or more of the plurality of transfer devices.
35. The method of claim 21, further comprising:
implanting, with two boron implants, a second plurality of p-type regions in which the plurality of reset devices is formed.
36. The method of claim 21, further comprising:
implanting, with two boron implants, a second plurality of p-type regions in which the plurality of reset devices is formed, wherein the first boron implant has a first energy range of 40 to 60 keV and a first dose range of 1.5\xd71012 to 2.0\xd71012 atomscm2, and the second boron implant has a second energy range of 180 to 220 keV and a second dose range of 1.0\xd71012 atomscm2 to 1.4\xd71012 atomscm2.
37. The method of claim 21, wherein each of the plurality of transfer devices includes a body connecting the first terminal and the second terminal such that the control terminal controls the transfer of the electrons between the first terminal and the second terminal through the body, and a dielectric between the control terminal and the body, the dielectric satisfying a lifetime specification of the image sensor integrated circuit when the control signal is applied with the channel formed, the dielectric failing the lifetime specification of the image sensor integrated circuit if the control signal is applied with at least one of the first terminal and the second terminal at a ground voltage of the image sensor integrated circuit.
38. The method of claim 21, wherein the plurality of signal devices includes a plurality of row select transistors coupled to the row and column circuitry and a plurality of source follower transistors coupled to the plurality of nodes.
39. The method of claim 21, wherein the plurality of photodetectors is a plurality of photodiodes.
40. The method of claim 21, wherein each measurement of the total of the photons is corrected by correlated multiple sampling with a prior measurement of the total of the photons.
41. A computer readable description of an image sensor integrated circuit comprising:
a plurality of photodetectors generating electrons excited by incident photons, each of the plurality of photodetectors including:
an n-type region receiving the electrons excited by the energy of the photons;
a plurality of nodes, wherein each of the plurality of photodetectors has a corresponding node of the plurality of nodes;
a plurality of transfer devices controlling a transfer of the electrons from said each of the plurality of photodetectors to the corresponding node, each of the plurality of transfer devices including:
a first terminal coupled to the n-type region of one of the plurality of photodetectors;
a second terminal coupled to one of the plurality of nodes; and
a control terminal receiving the control signal, wherein the transfer of the electrons occurs between the first terminal and the second terminal in response to a control signal of sufficient value applied to the control terminal;
a plurality of p-type regions having a concentration stronger than a background concentration, wherein each of the plurality of p-type regions has a lateral position at least partly under the control terminal of a transfer device of the plurality of transfer devices controlling the transfer of electrons from a photodetector of the plurality of photodetectors to the corresponding node of the photodetector, and each of the plurality of p-type regions has a lateral position at least partly under the corresponding node;
a plurality of reset devices, wherein each of the plurality of nodes has a corresponding reset device of the plurality of reset devices, and said each of the plurality of nodes is reset when the corresponding reset device is active;
row and column circuitry; and
a plurality of signal devices coupling the plurality of nodes to the row and column circuitry.