1. A semiconductor apparatus comprising:
a shift register adapted to pass a start signal therethrough in synchronization with a clock signal of a large amplitude level to sequentially generate a plurality of latch signals;
a data register adapted to latch sequential data signals of the large amplitude level in synchronization with said latch signals;
a data latch circuit adapted to latch all said sequential data signals latched in said data register in synchronization with a strobe signal; and
a receiver connected to said shift register and said data register, said receiver adapted to convert differential clock signals of a small amplitude level into said clock signal of the large amplitude level from a timing of generation of said strobe signal to a timing of completion of latching all said sequential data signals in said data register, and transmit said clock signal of the large amplitude level to said shift register, and adapted to convert differential data signals of the small amplitude level into said sequential data signals from a timing of generation of said start signal to the timing of completion of latching all said sequential data signals in said data register and transmit said sequential data signals to said data register.
2. The apparatus as set forth in claim 1, wherein said receiver comprises:
a clock signal receiver adapted to amplify the difference in voltage between said differential clock signals to generate said clock signal;
a data signal receiver adapted to amplify the difference in voltage between said differential data signals to generate said sequential data signal;
a first switch connected to said clock signal receiver and adapted to apply a first bias voltage to said clock signal receiver to activate said clock signal receiver;
a second switch connected to said data signal receiver and adapted to apply a second bias voltage to said data signal receiver to activate said data signal receiver;
a first control circuit connected to said first switch and adapted to turn ON said first switch from the timing of generation of said strobe signal to the timing of completion of latching all said sequential data signals; and
a second control circuit connected to said second switch and adapted to turn ON said second switch from the generation of said start signal to the timing of completion of latching all said-sequential data signals.
3. The apparatus as set forth in claim 1, being a data signal driver adapted to drive data lines of a liquid crystal display apparatus.
4. A semiconductor apparatus comprising a plurality of units connected to each other by a cascade connection and adapted to pass a start signal therethrough, each of said units comprising;
a shift register adapted to pass said start signal therethrough in synchronization with a clock signal of a large amplitude level to sequentially generate a plurality of latch signals;
a data register adapted to latch sequential data signals of the large amplitude level in synchronization with said latch signals;
a data latch circuit adapted to latch all said sequential data signals latched in said data register in synchronization with a strobe signal; and
a receiver connected to said shift register and said data register, said receiver adapted to convert differential clock signals of a small amplitude level into said clock signal of the large amplitude level from a timing of generation of said strobe signal to a timing of completion of latching all said sequential data signals in said data register, and transmit said clock signal of the large amplitude level to said shift register, and adapted to convert differential data signals of the small amplitude level into said sequential data signals from a timing of generation of said start signal to the timing of completion of latching all said sequential data signals in said data register and transmit said sequential data signals to said data register.
5. The apparatus as set forth in claim 4, wherein said receiver comprises:
a clock signal receiver adapted to amplify the difference in voltage between said differential clock signals to generate said clock signal;
a data signal receiver adapted to amplify the difference in voltage between said differential data signals to generate said sequential data signal;
a first switch connected to said clock signal receiver and adapted to apply a first bias voltage to said clock signal receiver to activate said clock signal receiver;
a second switch connected to said data signal receiver and adapted to apply a second bias voltage to said data signal receiver to activate said data signal receiver;
a first control circuit connected to said first switch and adapted to turn ON said first switch from the timing of generation of said strobe signal to the timing of completion of latching all said sequential data signals; and
a second control circuit connected to said second switch and adapted to turn ON said second switch from the generation of said start signal to the timing of completion of latching all said sequential data signals.
6. The apparatus as set forth in claim 4, wherein each of said units is a data signal driver adapted to drive data lines of a liquid crystal display apparatus.
7. A receiver of a source driver, comprising;
a first receiving circuit receiving a clock signal;
a plurality of second receiving circuits each receiving a data signal;
a bias circuit for producing a bias voltage;
a first switch coupled between said bias circuit and said first receiving circuit and controlled by a first control signal to apply said bias voltage to said first receiving circuit; and
a second switch coupled between said bias circuit and said second receiving circuits and controlled by a second control signal different from said first control signal to apply said bias voltage to said second receiving circuits.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A flexible wired circuit board having a plurality of layers formed in a generally rectangular, flat, strip-shape, and having a generally narrow central portion and relatively rectangular, flat, widened end portions, for temperature measurement said layers comprising:
a conductor layer; and
a base insulating layer formed on one side of said conductor layer;
wherein the conductor layer is formed from a metal foil having a proportional relation between temperature and specific electric resistance;
wherein said conductor layer includes a temperature detecting portion formed when said conductor layer is formed as a wiring portion and arranged in a predetermined pattern on said base insulating layer; and
wherein the temperature detecting portion is formed on the base insulating layer at one of the generally rectangular, flat, widened end portions of the base insulating layer.
2. The flexible wired circuit board for temperature measurement according to claim 1, wherein the conductor layer is a stainless foil.
3. The flexible wired circuit board for temperature measurement according to claim 1, wherein said wiring portion includes a wiring folded in such a continuous form that adjacent parts of the wiring extending in parallel are spaced apart from each other at a predetermined interval.
4. The flexible wired circuit board for temperature measurement according to claim 3, wherein the wiring in the temperature detecting portion has an entire length of 50 mm or more.
5. The flexible wired circuit board for temperature measurement according to claim 3, wherein the adjacent parts of the wiring in the temperature detecting portion are spaced apart from each other at a pitch of 100 \u03bcm or more.
6. A flexible wired circuit board having a plurality of layers formed in a generally rectangular, flat, strip-shape, and having a generally narrow central portion and relatively rectangular, flat, widened end portions, for temperature measurement, said layers comprising:
a conductor layer formed from a stainless foil;
a base insulating layer formed from a polyimide film formed on one side of said conductor layer;
a cover insulating layer from a polyimide film, and formed on another side of said conductor layer;
wherein said conductor layer, comprising a main wiring portion for wiring and a sensor-wiring portion, including a temperature detecting portion, is formed in one piece in a form of a predetermined pattern; and
wherein the temperature detecting portion is formed on the base insulating layer at one of the generally rectangular, flat, widened end portions of the base insulating layer.