1. A system for error correction of a pipeline analog to digital converter (\u201cADC\u201d), wherein the pipeline ADC converts a voltage signal to a digital version of the voltage signal, comprising:
a coarse ADC wherein an input terminal of the coarse ADC receives the voltage signal and a reference signal and provides a digital version of the voltage signal value relative to the reference signal to a digital to analog converter (\u201cDAC\u201d)
input terminal;
a first adder for combining the voltage signal and an output signal from the DAC, wherein the first adder result is provided to a residue amplifier;
a backend ADC, wherein the backend ADC provides a digital version of an output voltage signal received from the residue amplifier;
a second adder for summing digital values received from the coarse ADC, a digital to analog converter noise cancellation (\u201cDNC\u201d) circuit, and a harmonic distortion correction (\u201cHDC\u201d) circuit, thereby providing a pipelined ADC output;
a circuit for estimating distortion parameters from the residue amplifier and digital to analog converter comprising:
the HDC, wherein the HDC, responsive to the pipelined ADC output, corrects distortion components due to the residue amplifier present in the digital signal from the backend ADC; and
the DNC circuit, wherein the DNC circuit, responsive to the pipelined ADC output, corrects the distortion components due to the DAC present in the digital signal from the backend ADC; and
a circuit for modifying the reference signal to the coarse analog to digital converter.
2. The system of claim 1, wherein the circuit for modifying the reference signal comprises:
a voltage divider for dividing a reference source voltage;
a dynamic element matching (\u201cDEM\u201d) circuit receiving the divided voltage signals, each divided voltage signal connected to a corresponding switch, wherein each switch is controlled by the DEM circuit and further wherein all output terminals from the switches are connected in parallel to a first side of a high side capacitor; and
a sequences adder block receiving HDC signals, each HDC signal connected to a corresponding switch, wherein each switch is controlled by the HDC circuit and further wherein all output terminals from the switches are connected in parallel to a second side of the high side capacitor.
3. The system of claim 1, wherein the ADC and the DAC are n bit devices.
4. A pipeline analog-to-digital (ADC) converter, comprising:
a back end analog-to-digital (ADC) converter configured to receive a residue output; and
at least one stage circuit, the stage circuit comprising;
a coarse ADC coupled to receive an input signal and provide a coarse digital output to a digital-to-analog (DAC) converter;
a residue amplifier configured to receive the input signal and an output of the DAC and provide a residue output to the backend ADC;
a circuit for estimating distortion parameters from the residue amplifier and DAC, comprising:
an amplifier configured to receive an output of the backend DAC;
a harmonic distortion correction circuit (HDC) coupled to the amplifier and configured to correct distortion components due to the residue amplifier present in the digital signal from the backend ADC, the HDC circuit providing an output to an adder, the adder receiving the coarse digital output; and
a DAC noise cancellation circuit (DNC) configured to provide an output to the adder, wherein the DNC circuit is configured to correct the distortion components due to the DAC present in the digital signal from the backend ADC;
wherein the output of the adder is an ADC digital output and wherein the ADC digital output forms an input to the HDC and the DNC; and
a circuit for modifying a reference signal to the coarse ADC.
5. The pipeline analog-to-digital (ADC) converter of claim 4, wherein the circuit for modifying the reference signal comprises:
a voltage divider for dividing a reference source voltage into a plurality of divided voltage signals;
a dynamic element matching (\u201cDEM\u201d) circuit receiving the divided voltage signals, each divided voltage signal connected to a corresponding switch, wherein each switch is controlled by the DEM circuit and further wherein all output terminals from the switches are connected in parallel to a first side of a high side capacitor; and
a sequences adder block receiving HDC signals, each HDC signal connected to a corresponding switch, wherein each switch is controlled by the HDC circuit and further wherein all output terminals from the switches are connected in parallel to a second side of the high side capacitor.
6. The pipeline analog-to-digital (ADC) converter of claim 5, wherein the ADC and the DAC are n bit devices.
7. A pipeline analog-to-digital converter (ADC) for converting an input signal, comprising:
a coarse analog-to-digital converter (ADC) configured to provide a coarse digital output to a digital-to-analog converter (DAC);
a residue amplifier configured to receive an output of the DAC and the input signal and generate a residue for a next pipeline stage;
a circuit for estimating distortion parameters from a residue amplifier and the DAC, the circuit including:
a harmonic distortion correction (HDC) circuit configured to provide an output to an adder, the adder receiving as an input an output of the coarse ADC; and
a feedback loop including a DAC noise cancellation (DNC) circuit configured to provide an output to the adder;
wherein an output of the adder is an ADC digital output and is an input to the DNC circuit; and
a circuit for modifying a reference signal to the coarse ADC.
8. The pipeline analog-to-digital converter (ADC) of claim 7, wherein the HDC circuit is configured to receive one or more random sequences for estimating nonlinearities.
9. The pipeline analog-to-digital converter (ADC) of claim 8, wherein the HDC circuit is configured to provide an output to the circuit for modifying the reference signal to the coarse ADC.
10. The pipeline analog-to-digital converter (ADC) of claim 8, wherein the circuit for modifying the reference signal comprises:
a voltage divider for dividing a reference source voltage;
a dynamic element matching (\u201cDEM\u201d) circuit receiving the divided voltage signals, each divided voltage signal connected to a corresponding switch, wherein each switch is controlled by the DEM circuit and further wherein all output terminals from the switches are connected in parallel to a first side of a high side capacitor; and
a sequences adder block receiving HDC signals, each HDC signal connected to a corresponding switch, wherein each switch is controlled by the HDC circuit and further wherein all output terminals from the switches are connected in parallel to a second side of the high side capacitor.
11. A method for operating a pipeline analog-to-digital converter (ADC) for converting an input signal, comprising:
providing a coarse digital output from a coarse analog-to-digital converter (ADC) to a digital-to-analog converter (DAC)
receiving an output of the DAC and the input signal at a residue amplifier and generating a residue for a next pipeline stage;
estimating distortion parameters from the residue amplifier output and the DAC output, the estimating including:
performing a harmonic distortion correction as an output to an adder, the adder receiving as another input an output of the coarse ADC; and
implementing a feedback loop including a DAC noise cancellation (DNC) providing an output to the adder;
wherein an output of the adder is an ADC digital output and is an input to the DNC circuit.
12. A method for operating a pipeline analog-to-digital converter (ADC) for converting an input signal in accordance with claim 11, further including modifying a reference signal to the coarse ADC.
13. A method for operating a pipeline analog-to-digital converter (ADC) for converting an input signal in accordance with claim 11, wherein the HDC circuit receives one or more random sequences for estimating nonlinearities.
14. A method for operating a pipeline analog-to-digital converter (ADC) for converting an input signal in accordance with claim 13, wherein the HDC circuit provides an output to the circuit for modifying the reference signal to the coarse ADC.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
The embodiments of an invention in which an exclusive property or right is claimed are defined as follows:
1. A method of forming a composite diaphragm for a pressure device, the method comprising the steps of:
providing a substrate layer having a first conductivity type, the substrate layer having a first surface;
depositing implants in the first surface of the substrate layer;
growing an epitaxial layer on the first surface of the substrate layer, the implants forming diffusions in the epitaxial layer;
forming an oxide pattern on the epitaxial layer;
depositing a top layer over the epitaxial layer and oxide pattern; and
etching the substrate layer and diffusions of the epitaxial layer to form the composite diaphragm.
2. The method of claim 1, wherein the implants are positive implants and the diffusions are positive diffusions.
3. The method of claim 1, in which the substrate layer comprises a p-type single crystal silicon material.
4. The method of claim 1, in which the positive implants are deposited using an ion implanter.
5. The method of claim 1, in which the top layer comprises silicon nitride.
6. The method of claim 5, in which the substrate layer comprises a p-type single crystal silicon material.
7. The method of claim 1, in which the etching step comprises a stop-etch process.
8. The method of claim 2, in which portions of the epitaxial layer not formed with the positive diffusions form a pattern.
9. The method of claim 8, in which the pattern comprises a plurality of bosses.
10. The method of claim 9, in which the pattern further comprises a plurality of battens extending between adjacent bosses.
11. The method of claim 10, in which the substrate layer comprises a p-type single crystal silicon material.
12. The method of claim 10, in which the top layer comprises silicon nitride.
13. The method of claim 12, in which the substrate layer comprises a p-type single crystal silicon material.
14. A composite diaphragm for use in a pressure device, the diaphragm comprising:
a first layer of silicon nitride; and
a second layer attached to the silicon nitride layer and comprising a pressure sensor pattern of silicon material.
15. The diaphragm of claim 14, further comprising a third layer intermediate the first and second layers, wherein the third layer comprises an epitaxial layer of single crystal silicon.
16. The diaphragm of claim 15, further comprising a patterned oxide layer deposited between the second and third layers.
17. The diaphragm of claim 14, in which the second layer comprises a p-type single crystal silicon.
18. The diaphragm of claim 14, in which the pattern comprises a plurality of bosses.
19. The diaphragm of claim 18, in which the pattern further comprises a plurality of battens extending between adjacent bosses.
20. The diaphragm of claim 19, in which each batten includes a pair of intersecting leg portions and a pair of connecting portions adapted to engage adjacent bosses.
21. The diaphragm of claim 14, wherein the second layer comprises a pressure sensor pattern of single crystal silicon.
22. A silicon based diaphragm for a piezoresistor capable of producing a usable, substantially linear output signal at less than 5 inches of H2O of input pressure.
23. The silicon based diaphragm of claim 22 being capable of producing the usable, substantially linear output signal substantially through a range of 0 to 5 inches of H2O of input pressure.
24. The silicon based diaphragm of claim 22 comprising a silicon nitride layer abutting a single crystal silicon layer.
25. The silicon based diaphragm of claim 22 being capable of producing the usable, substantially linear output signal substantially through a range of 0 to 5 inches of H2O of input pressure.
26. A method of forming a composite diaphragm for a pressure device, the method comprising the steps of:
providing a substrate layer having a first conductivity type, the substrate layer having a first surface;
depositing positive implants in the first surface of the substrate layer;
growing an epitaxial layer on the first surface of the substrate layer, the positive implants forming positive diffusions in the epitaxial layer;
forming an oxide pattern on the epitaxial layer;
depositing a silicon nitride layer over the epitaxial layer and oxide pattern; and
etching the substrate layer and diffusions of the epitaxial layer to form the composite diaphragm.