1. A digital duty cycle correction (DCC) circuit, comprising:
a first conversion circuit for buffering an internal clock output from a delay locked loop (DLL), converting the buffered internal clock into first and second clocks through first and second terminals, delaying the second clock according to voltage supplied to the second terminal through a capacitor, converting the delayed second clock into a first signal, and converting the first clock into a third clock, which rises at a falling edge of the first clock and falls at a rising edge of the first signal; and
a second conversion circuit for converting the third clock into an output clock, which rises at a falling edge of the third clock and falls at a rising edge of the third clock.
2. The duty cycle correction circuit of claim 1, wherein the first conversion circuit comprises:
a first inverter for converting the internal clock into the first clock;
a second inverter for converting the internal clock into the second clock;
a capacitor for supplying the voltage to the second terminal, that is, an output of the second inverter; and
a logic element for combining the first clock and an output of the second inverter and outputting the third clock.
3. The duty cycle correction circuit of claim 1, wherein the second conversion circuit comprises a flip-flop for generating the output clock by using the third clock and the first signal as inputs.
4. The duty cycle correction circuit of claim 2, wherein the first conversion circuit further comprises a capacitor for supplying a second voltage different from the voltage to the second terminal, that is, an output of the second inverter.
5. The duty cycle correction circuit of claim 1, wherein the voltage supplied to the second terminal through the capacitor is generated by:
a phase divider for generating second and third signals having opposite phases in response to the output clock from the second conversion circuit;
a compare control unit for generating a pump reset signal and a compare control signal in response to the output clock;
a duty cycle correction pump for pumping the second and third signals and generating a first pumping clock and a second pumping clock, in response to the pump reset signal;
a voltage comparator for sensing the compare control signal and voltage levels of the first and second pumping clocks, and generating an incrementdecrement signal;
a counter for outputting a counter signal in response to the incrementdecrement signal; and
a voltage generator operating in response to the counter signal.
6. The duty cycle correction circuit of claim 5, wherein the duty cycle correction pump determines duty mismatch by comparing the first clock and the second clock, pumps the first clock and the second clock to a specific level or more or less, and outputs the first pumping clock and the second pumping clock.
7. The duty cycle correction circuit of claim 5, wherein the voltage comparator determines a level of an increase or decrease of a high pulse width by comparing levels of the first pumping clock and the second pumping clock in response to the compare control signal, and outputs a signal that increases or decreases to the counter.
8. The duty cycle correction circuit of claim 7, wherein the voltage comparator outputs the increment signal when the level of the first pumping clock is higher than a specific level, and outputs the decrement signal when the level of the first pumping clock is lower than a specific level.
9. The duty cycle correction circuit of claim 5, wherein the counter converts bits of the increment and decrement signals into a binary number, and outputs a converted binary number as the counter signal.
10. A digital duty cycle correction (DCC) circuit of a delay locked loop (DLL), comprising:
a duty correction circuit for correcting a duty of a internal clock and outputting an output clock;
a phase divider for generating a first clock having the same phase as that of the output clock and a second clock having an opposite phase to that of the first clock in response to the output clock;
a compare control unit for generating a pump reset signal and a compare control signal in response to the output clock;
a DCC pump for pumping the first clock and the second clock and generating a first pumping clock and a second pumping clock in response to a pump reset signal;
a voltage comparator for sensing the compare control signal and the voltage levels of the first pumping clock and the second pumping clock and generating an incrementdecrement signal;
a counter for outputting a counter signal in response to the incrementdecrement signal; and
a voltage generator for generating a voltage in response to the counter signal.
11. The digital duty cycle correction circuit of claim 10, wherein the duty correction circuit comprises:
a buffer unit for receiving the internal clock, buffering the received internal clock, and outputting a first input clock and a second input clock;
a delay control unit for controlling the delay of the second input clock according to the at least one voltage generated by the voltage generator, and generating a delay signal;
a NAND gate for outputting a first logic signal in response to the first input clock and the delay signal; and
a flip-flop unit for generating an output clock having a corrected duty cycle in response to the first logic signal and the delay signal.
12. The digital duty cycle correction circuit of claim 11, wherein the delay control unit comprises a plurality of capacitors.
13. The digital duty cycle correction circuit of claim 12, wherein the plurality of capacitors are formed of metal oxide semiconductor (MOS) transistors.
14. The digital duty cycle correction circuit of claim 11, wherein the flip-flop unit comprises:
a first NAND gate for generating a second logic signal in response to the delay signal and the output clock; and
a second NAND gate for generating the output clock in response to the first logic signal and the second logic signal.
15. The digital duty cycle correction circuit of claim 10, wherein the DCC pump receives the first and second clocks, determines duty cycle mismatch, pumps the first and second clocks to a specific level, and outputs the first pumping clock and the second pumping clock.
16. The digital duty cycle correction circuit of claim 10, wherein the voltage comparator compares levels of the first and second pumping clocks applied thereto, determines an increase or reduction of a pulse width, and outputs the incrementdecrement signal representing an increase or a decrease, in response to the compare control signal.
17. The digital duty cycle correction circuit of claim 16, wherein the voltage comparator outputs the incrementdecrement signal representing an increase when the first pumping clock applied thereto is higher than a specific level, and outputs the incrementdecrement signal representing a decrease when the first pumping clock applied thereto is lower than the specific level.
18. The digital duty cycle correction circuit of claim 10, wherein the counter converts the incrementdecrement signal into a binary number and outputs the result as the counter signal.
19. The digital duty cycle correction circuit of claim 10, wherein the compare control unit outputs a first control signal and a second control signal in order to control a delay time of the duty correction circuit.
20. The digital duty cycle correction circuit of claim 10, wherein the voltage generator generates one or more voltages in order to control an amount of correction of the duty correction circuit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A nuclear magnetic resonance imaging radio frequency receiver the receiver being adapted to receive analogue signals from at least one radio frequency receiver coil unit, the radio frequency receiver comprising:
an analogue-digital converter for converting the analogue pre-amplified magnetic resonance signal into a digital signal,
means for digital down converting the digital signal and
a first communication interface adapted for transmitting the down converted digital signal via a communication link.
2. The receiver of claim 1, further comprising a local clock oscillator.
3. The receiver of claim 2, wherein the local clock oscillator is synchronizable by a pilot tone signal, the pilot tone signal being generated by a pilot tone transmit coil or wherein the local clock oscillator is synchronizable by a system clock.
4. The receiver of claim 1, further comprising means for encoding andor compressing the down converted digital signal.
5. The receiver of claim 1, wherein the receiver is comprised in the radio frequency receiver coil unit.
6. The receiver of claim 1, further comprising merging means, wherein the merging means are adapted to combine multiple digitized magnetic resonance signals and control and status signals for controlling the receiver, the multiple digitized magnetic resonance signals originating from multiple antenna elements of the receiver coil unit.
7. The receiver of claim 1, further comprising an electronic testing circuit, wherein the electronic test circuit is adapted for examining the electronic components of the radio frequency receiver, wherein the examination is being performable using a test coil, said test coil being adapted in the radio frequency receiver coil unit.
8. The receiver of claim 1, further comprising means for spike detection and removal in the digitized radio frequency signal.
9. The receiver of claim 1, wherein the first communication interface is adapted for providing the digitized signal via the communication link by wireless radio frequency transmission or optical transmission or wired transmission.
10. A magnetic resonance imaging apparatus, comprising a nuclear magnetic resonance imaging radio frequency receiver according to any of the previous claims, the apparatus further comprising:
at least one radio frequency receiver coil unit,
a main magnet adapted for generating a main magnetic field,
magnetic field gradient coils adapted for selectively generating magnetic field gradients to be superimposed to the main magnetic field,
a radio frequency transmit coil for generating a radio frequency pulse sequence
a second communication interface, said second communication interface being adapted for communication with the first communication interface and
a control and data acquisition system, wherein the control and data acquisition system is adapted for communicating with the receiver using the second communication interface.
11. An RF interface structure for a magnetic resonance imaging system comprising:
at least one receiver according to claim 1,
a second communication interface, said second communication interface being adapted for communication with the first communication interface of the receiver
merging means, wherein the merging means are adapted to combine multiple signals being communicated over multiple second communication interfaces, said multiple signals being communicated to or from multiple radio frequency receiver coil units using multiple receivers,
a radio frequency scan control unit, said radio frequency scan control unit being adapted for controlling the at least one receiver.
12. A control and data acquisition system comprising means for generation of pulse sequences andor control commands, said pulse sequences andor control commands being adapted to control an RF interface structure, said slave system comprising a receiver according to claim 1.
13. A method for receiving a radio frequency signal from a magnetic resonance imaging receiver coil unit, the method comprising:
receiving an analogue pre-amplified magnetic resonance signal from the receiver coil unit,
converting the analogue signal into a digital signal,
digital down converting the digital signal and
communicating the digital down converted signal over a first communication interface.