1. A method of promoting hair growth in a subject, the method comprising:
delivering to the subject at least 5 mg of fulvic acid per day.
2. The method according claim 1, wherein the fulvic acid is purified or substantially purified.
3. The method according to claim 2, wherein the fulvic acid is purified or substantially purified using a XAD-8.
4. The method according to claim 2, wherein the fulvic acid is purified or substantially purified from an aquatic source.
5. The method according to claim 2, wherein the fulvic acid is not purified or substantially purified from coal, shilajit, or peat.
6. The method according to claim 1, wherein the fulvic acid is not oxifulvic acid.
7. The method according to claim 1, wherein from 20 to 30 mg of fulvic acid is delivered to the subject per day.
8. The method according to claim 1, wherein 25 mg of fulvic acid is delivered to the subject per day.
9. A composition for human use, the composition comprising at least 700 mgL fulvic acid.
10. The composition of claim 9, wherein the composition is in a form selected from the group consisting of tablets, capsules, granules, sprays, inhalers, suppositories, sprays, patches, balms, drops, cosmetics, supplements, foods, creams, ointments, liquids, drinks, beverages, lotions, milky lotions, facial packs, bathing agents, bath detergents, facial cleansing agents, shaving creams, hair lotions, hair-care compositions, and shampooing agents.
11. The composition of claim 9, wherein the composition further comprises a carrier or an adjuvant.
12. The composition of claim 9, wherein the composition comprises from 700 to 20,000 mgL fulvic acid.
13. The composition of claim 9, wherein the composition comprises from 700 to 1000 mgL fulvic acid.
14. The composition of claim 9, wherein the composition comprises 3000 mgL fulvic acid.
15. The composition of claim 9, wherein the fulvic acid is purified or substantially purified.
16. The composition of claim 9, wherein the fulvic acid is purified or substantially purified using XAD-8.
17. The composition of claim 16, wherein the fulvic acid is purified or substantially purified from an aquatic source.
18. The composition of claim 16, wherein the fulvic acid is not purified or substantially purified from coal, shilajit, or peat.
19. The composition of claim 9, wherein the fulvic acid is not oxifulvic acid.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A processor comprising:
a first set of registers allocated to a first process;
a circuit to selectively store contents of a first subset of the first set of registers to a memory upon making current a second process, wherein the stored contents of the first subset of the first set of registers are modified registers during the first process.
2. The processor of claim 1 wherein the circuit loads a second subset of the first set of registers for the second process, where the second subset of the first set of registers are non-modified registers during the first process.
3. The processor of claim 2 wherein the circuit initiates a miss signal when the second process requests the modified registers of the first process.
4. The processor of claim 3 wherein the circuits loads the modified registers to a register file upon receiving the miss signal.
5. The processor of claim 1 wherein each register in the first set of registers includes a valid bit, a poison bit and a modify bit.
6. The processor of claim 5 wherein the valid bit indicates if the register in a register file is valid.
7. The processor of claim 5 wherein the poison bit indicates if the register is to be reissued.
8. The processor of claim 5 wherein the modify bit indicates if the register has been written to in the first process.
9. A method comprising:
allocating a first set of registers for a first process;
storing content of a first subset of the first set of registers;
switching to a second process;
requesting the content of the first subset of the first set of registers by the second process; and
reading content of the first subset of the first set of registers upon request by the second process.
10. The method of claim 9 wherein said storing includes saving valid, poison and modify bits stored therein.
11. The method of claim 10 wherein said requesting includes determining if valid bit is set for the requested registers.
12. The method of claim 11 wherein said determining includes incurring a miss if valid bit is not set and setting the poison bit.
13. The method of claim 12 wherein said incurring includes sending a signal to an instruction queue to indicate a miss flow for the register.
14. The method of claim 13 wherein said sending includes finding new architectural register for the register incurring a miss.
15. The method of claim 14 wherein said sending includes issuing the new register value to an execution unit.
16. The method of claim 15 wherein said issuing includes writing the new register value to the architectural register and setting the valid bit.
17. The method of claim 16 wherein said setting the valid bit includes reissuing the requested register.
18. A system comprising:
A processor including a first set of registers allocated to a first process, and a circuit to selectively store contents of a first subset of the first set of registers to a memory upon making current a second process, wherein the stored contents of the first subset of the first set of registers are modified registers during the first process;
an interconnect to couple the processor to inputoutput devices; and
an audio inputoutput device coupled to the interconnect and to the processor.
19. The system of claim 18 wherein the circuit loads a second subset of the first set of registers for the second process, where the second subset of the first set of registers are non-modified registers during the first process.
20. The system of claim 19 wherein the circuit initiates a miss signal when the second process requests the modified registers of the first process.
21. The system of claim 20 wherein the circuits loads the modified registers to a register file upon receiving the miss signal.
22. The system of claim 21 wherein each register in the first set of registers includes a valid bit, a poison bit and a modify bit.
23. The system of claim 22 wherein the interconnect is a point to point interconnect.