1. In a computing system for handling freehand drawn lines and shapes, a method for improving the appearance of the hand drawn lines and shapes comprising:
comparing a source line segment of a source line against a straight line and detecting a deviation value indicating deviation between the source line segment and the straight line;
straightening the source line segment to a straight line if the deviation value is below a predetermined threshold value;
evaluating the source line segment as an angle segment, when the deviation value is below a predetermined threshold value, by detecting whether the source line segment can be defined as an angle segment with two straight line segments and defining the line segment as an angle segment having two straight line segments intersecting at an angle if the source line segment can be defined with two straight line segments;
dividing the source line segment into new segments if the deviation value is not below the predetermined threshold value and the line segment can not be defined as an angle segment; and
repeating the acts of comparing, straightening, evaluating and dividing on the new segments until all segments of the source line have been straightened.
2. The method of claim 1 further comprising:
detecting if the source line closes on itself and thereby forms a shape;
improving the shape to a polyline shape if the source line closes on itself; and
improving the source line to a polyline if the source line does not close on itself.
3. The method of claim 2 further comprising:
comparing the polyline shape against reference shapes and improving the polyline shape to a reference shape most similar to the polyline shape.
4. The method of claim 1 wherein the act of detecting comprises:
finding a point of intersection between a first source line segment and a second source line segment making up the angle segment;
comparing the first source line segment to a straight line to determine if its deviation is below the predetermined threshold; and
comparing the second source line segment to a straight line to determine if its deviation is below the predetermined threshold.
5. The method of claim 4 wherein the act of defining comprises:
straightening the first line segment to a straight line and the second line segment to a straight line intersecting at the point of intersection if both the first and second source line segments have a deviation from a straight line below the predetermined threshold.
6. The method of claim 5 further comprising:
combining line segments and angle segments to form a polyline; and
detecting if the polyline line closes on itself and thereby forms a polyline shape.
7. The method of claim 6 further comprising:
comparing the polyline shape against basic reference shapes and improving the polyline shape to a transformed shape transformed from a basic shape most similar to the polyline shape; and
adjusting the transformed shape to a specific shape identified from the basic shape.
8. In a computing system, apparatus for reshaping freehand drawn source lines into a polyline, the apparatus comprising:
a segment compare module comparing a source line segment of a source line against a straight line and detecting a deviation value indicating deviation between the source line segment and the straight line;
a define line segment module straightening the source line segment to a straight line if the deviation value detected by the compare module is within a deviation threshold value indicating the source line segment is a straight line segment;
an evaluate module evaluating the source line segment as an angle segment, when the compare module detects the deviation value exceeds the deviation threshold value, the evaluate module detecting whether or not the source line segment has two straight line segments or more than two straight line segments;
a define angle segment module defining the source line segment as an angle segment made up of two straight lines intersecting at a point if the evaluate module detects two straight line segments;
a divide module dividing the source line segment into new source line segments if the evaluate module detects more than two straight line segments; and
each of the new source line segments being processed by the segment compare module and the evaluate module until the source line has been reshaped into a polyline.
9. The apparatus of claim 8 further comprising:
a polyline test module detecting if the polyline closes on itself and thereby forms a polyline shape.
10. The apparatus of claim 8 wherein the evaluate module comprises:
a intersection module finding a point of intersection between a first source line segment and a second source line segment making up the source line segment;
a split module splitting the source line segment at the point of intersection into the first source line segment and the second source line segment;
first split compare module comparing the first source line segment to a straight line to determine if its deviation is below the deviation threshold value;
second split compare module comparing the second source line segment to a straight line to determine if its deviation is below the deviation threshold value; and
a segment test module detecting that both the first and second source line segments have a deviation from a straight line below the deviation threshold value and generating a angle segment true condition indicating detection of an angle segment, and the segment test module detecting that at least one of the first and second source line segments have a deviation from a straight line exceeding the deviation threshold value, and generating an angle segment fail condition.
11. The apparatus of claim 10 wherein the define angle segment module is responsive to the angle segment true condition to straighten the first line segment to a straight line and the second line segment to a straight line intersecting at the point of intersection.
12. The apparatus of claim 10 wherein the divide module is responsive to the angle segment fail condition to divide the source line segment into two new source line segments for processing by the segment compare module and the evaluate module.
13. The apparatus of claim 8 further comprising:
a combine module combining straight lines from the define line module and angle segments from the define angle segment module to form a polyline.
14. The apparatus of claim 13 further comprising:
a closed line test module detecting if the polyline line closes on itself and thereby forms a polyline shape.
15. A computer program product readable by a computing system and encoding a computer program of instructions for executing a computer process for improving the appearance of the hand drawn lines and shapes comprising:
comparing a source line segment of a source line input into the computing system against a straight line and detecting a deviation value indicating deviation between the source line segment and the straight line;
straightening the source line segment to a straight line if the deviation value is below a predetermined threshold value;
evaluating the source line segment as an angle segment, when the deviation value is below a predetermined threshold value, by detecting whether the source line segment can be defined as an angle segment with two straight line segments and defining the line segment as an angle segment having two straight line segments intersecting at an angle if the source line segment can be defined with two straight line segments;
dividing the source line segment into new segments if the deviation value is not below the predetermined threshold value and the line segment can not be defined as an angle segment; and
repeating the acts of comparing, straightening, evaluating and dividing on the new segments until all segments of the source line have been straightened.
16. The computer program product of claim 15 wherein the computer process further comprises:
detecting if the source line closes on itself and thereby forms a shape;
improving the shape to a polyline shape if the source line closes on itself; and
improving the source line to a polyline if the source line does not close on itself.
17. The computer program product of claim 16 wherein the computer process further comprises:
comparing the polyline shape against reference shapes and improving the polyline shape to a reference shape most similar to the polyline shape.
18. The computer program product of claim 15 wherein the act of detecting in the computer process comprises:
finding a point of intersection between a first source line segment and a second source line segment making up the angle segment;
comparing the first source line segment to a straight line to determine if its deviation is below the predetermined threshold; and
comparing the second source line segment to a straight line to determine if its deviation is below the predetermined threshold.
19. The computer program product of claim 18 wherein the act of defining in the computer process comprises:
straightening the first line segment to a straight line and the second line segment to a straight line intersecting at the point of intersection if both the first and second source line segments have a deviation from a straight line below the predetermined threshold.
20. The computer program product of claim 15 wherein the computer process further comprises:
combining line segments and angle segments to form a polyline; and
detecting if the polyline line closes on itself and thereby forms a polyline shape.
21. The computer program product of claim 20 wherein the computer process further comprises:
comparing the polyline shape against basic reference shapes and improving the polyline shape to a transformed shape transformed from a basic shape most similar to the polyline shape; and
adjusting the transformed shape to a specific shape identified from the basic shape.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A dynamic random access memory (DRAM), comprising:
a substrate, having a trench and a deep trench located on one side of the trench;
a vertical transistor, a portion of which being disposed in the trench and another portion disposed over the substrate, the vertical transistor comprising:
a gate structure, disposed in the trench and located over the substrate;
a first doped region, disposed in the substrate on sidewalls and bottom of the trench; and
a second doped region, disposed in the substrate on top of the trench;
a deep trench capacitor, disposed in the deep trench, comprising:
a bottom electrode, disposed in the substrate on a bottom of the deep trench;
a capacitor dielectric layer, disposed on sidewalls and the bottom of the deep trench; and
an upper electrode, disposed in the deep trench and located on the capacitor dielectric layer; and
a buried strap, disposed in the substrate below the vertical transistor, adjoining to the first doped region and the upper electrode.
2. The DRAM as claimed in claim 1, wherein the gate structure comprises:
a gate, disposed on the substrate, filling the trench; and
a gate dielectric layer, disposed between the gate and the substrate.
3. The DRAM as claimed in claim 2, wherein the material of the gate dielectric layer comprises silicon oxide.
4. The DRAM as claimed in claim 1, wherein the buried strap comprises a buried doped region.
5. The DRAM as claimed in claim 1, wherein the buried strap is formed by performing a thermal diffusion process.
6. The DRAM as claimed in claim 1, further comprising a channel doped region disposed between the first doped region and the second doped region, and located in the substrate on sidewalls of the trench.
7. The DRAM as claimed in claim 1, further comprising a dielectric layer disposed between the gate structure and the first doped region.
8. The DRAM as claimed in claim 1, wherein the upper electrode comprises:
a first conductive layer, disposed on the bottom of the deep trench;
a second conductive layer, disposed on the first conductive layer; and
a third conductive layer, disposed on the second conductive layer, wherein a surface thereof is below the bottom of the trench.
9. The DRAM as claimed in claim 1, wherein the deep trench capacitor further comprises a collar dielectric layer disposed on sidewalls of the trench above the first conductive layer, and surrounding the second conductive layer.
10. The DRAM as claimed in claim 9, wherein the material of the collar dielectric layer comprises silicon oxide.
11. The DRAM as claimed in claim 8, wherein the material of the first conductive layer, the second conductive layer and the third conductive layer comprise doped polysilicon.
12. A manufacturing method for DRAM, comprising:
providing a substrate having a deep trench;
forming a deep trench capacitor in the deep trench, wherein the deep trench
capacitor comprises a bottom electrode, an upper electrode and a capacitor dielectric layer;
removing a portion of the upper electrode of the deep trench capacitor to form a first trench;
forming a buried strap in the substrate on one side of the upper electrode;
forming an isolation structure in the first trench to define an active region;
removing a portion of the substrate adjacent to the isolation-structure to form a second trench;
forming a first heavily doped region on the bottom of the second trench, wherein the first heavily doped region is electrically connected to the buried strap;
forming a dielectric layer on the bottom of the second trench;
forming a first lightly doped region on sidewalls of the second trench, wherein the first lightly doped region is electrically connected to the first heavily doped region;
forming a second lightly doped region in the substrate, wherein the second lightly doped region is adjacent to the second trench;
forming a gate structure on top of the substrate, wherein the gate structure fills the second trench; and
forming a second heavily doped region in the substrate, wherein the second heavily doped region is electrically connected to the second lightly doped region.
13. The manufacturing method for DRAM as claimed in claim 12, wherein the method of forming the gate structure comprises:
forming a gate dielectric layer to conformally cover the whole substrate;
forming a conductive layer on the gate dielectric layer, wherein the conductive layer fills the trench; and
patterning the conductive layer and the gate dielectric layer.
14. The manufacturing method for DRAM as claimed in claim 13, wherein the material of the gate dielectric layer comprises silicon oxide.
15. The manufacturing method for DRAM as claimed in claim 12, wherein the buried strap comprises a buried doped region.
16. The manufacturing method for DRAM as claimed in claim 12, wherein the method of forming the buried strap comprises a thermal diffusion process.
17. The manufacturing method for DRAM as claimed in claim 12, further comprising a method of forming a channel doped region in the substrate on sidewalls of the trench after the step of forming the first lightly doped region but before the step of forming the second lightly doped region.
18. The manufacturing method for DRAM as claimed in claim 12, wherein the method of forming the deep trench capacitor in the deep trench comprises:
forming a bottom electrode in the substrate on bottom of the deep trench;
forming a capacitor dielectric layer on surface of the deep trench;
filling a first conductive layer on bottom of the deep trench;
removing the capacitor dielectric layer not covered by the first conductive layer;
forming a collar dielectric layer on sidewalls of the deep trench not covered by the first conductive layer;
filling a second conductive layer in the deep trench to cover the first conductive layer;
removing a portion of the second conductive layer and a portion of the collar dielectric layer to ensure a surface of the second conductive layer being lower than a surface of the substrate; and
filling a third conductive layer in the deep trench, wherein the first conductive layer, the second conductive layer and the third conductive layer form the upper electrode.
19. The manufacturing method for DRAM as claimed in claim 18, wherein the collar dielectric layer comprises silicon oxide.
20. The manufacturing method for DRAM as claimed in claim 18, wherein the material of the first conductive layer, the second conductive layer and the third conductive layer comprise doped polysilicon.
21. The manufacturing method for DRAM as claimed in claim 12, wherein a bottom of the second trench is above a surface of the upper electrode of the trench capacitor.
22. The manufacturing method for DRAM as claimed in claim 12, wherein the method of forming the second lightly doped region comprises a tilt-angle ion implantation process.