1. A process comprising:
determining a state of a CPU-enabled flag during execution of an idle thread by a central processing unit (CPU) in a plurality of central processing units in a symmetric multiprocessor system; and
shutting down said CPU during execution of said idle thread, upon said determining said state of said CPU-enabled flag finding that said state indicates said CPU is not logically enabled.
2. The process of claim 1 further comprising:
changing said state of said CPU-enabled flag from a first state to a second state, wherein said second state indicates that said CPU is not logically enabled.
3. The process of claim 2 further comprising:
setting said state of said CPU-enabled flag to said first state, wherein said first state indicates that said CPU is logically enabled.
4. The process of claim 2 further comprising:
setting an execution priority of said idle thread to a high idle execution priority.
5. The process of claim 1 further comprising:
setting said state of said CPU-enabled flag to a first state, wherein said first state indicates that said CPU is logically enabled.
6. A process comprising:
setting an execution priority of an idle thread to a high idle execution priority;
determining a state of a CPU-enabled flag, during execution of said idle thread, by a central processing unit (CPU) corresponding to said CPU-enabled flag wherein said CPU is in a plurality of central processing units in a symmetric multiprocessor system; and
shutting down said CPU during execution of said idle thread, upon said determining said state of said CPU-enabled flag finding that said state indicates said CPU is not logically enabled.
7. A process comprising:
setting a state of a CPU-enabled flag to a first state, wherein said first state indicates that a central processing unit (CPU) corresponding to said CPU-enabled flag is logically enabled, and further wherein said CPU is in a plurality of central processing units in a symmetric multiprocessor system;
setting an execution priority of an idle thread to a low idle execution priority;
determining said state of said CPU-enabled flag during execution of said idle thread by said CPU; and
shutting down said CPU during execution of said idle thread, upon said determining said state of said CPU-enabled flag finding that said state indicates said CPU is not logically enabled.
8. The process to claim 7 further comprising:
changing said state of said CPU-enabled flag from said first state to a second state, wherein said second state indicates that said CPU is not logically enabled.
9. The process of claim 7 further comprising:
changing said execution priority of said idle thread from said low idle execution priority to a high idle execution priority.
10. A process comprising:
setting a state of a CPU-enabled flag to a first state, wherein said first state indicates that a central processing unit (CPU) corresponding to said CPU-enabled flag is logically enabled, and further wherein said CPU is in a plurality of central processing units in a symmetric multiprocessor system;
setting an execution priority of an idle thread to a low idle execution priority;
changing said state of said CPU-enabled flag from said first state to a second state, wherein said second state indicates that said CPU is not logically enabled;
changing said execution priority of said idle thread from said low idle execution priority to a high idle execution priority;
determining a state of said CPU-enabled flag during execution of said idle thread by said CPU; and
shutting down said CPU during execution of said idle thread, upon said determining said state of said CPU-enabled flag finding that said state indicates said CPU is not logically enabled.
11. A process comprising:
determining an execution priority of an idle thread during execution of said idle thread by a central processing unit (CPU) in a plurality of central processing units in a symmetric multiprocessor system;
changing said execution priority from a normal idle execution priority to a shutdown priority; and
shutting down said CPU during execution of said idle thread, upon said determining said execution priority finding that said execution priority of said idle thread is said shutdown priority.
12. A structure comprising:
a plurality of central processing units in a symmetric multiprocessing system; and
a memory system coupled to said plurality of central processing units, said memory system further comprising:
a plurality of CPU-enabled flags wherein when a CPU-enabled flag for a central processing unit (CPU) has a first state, the CPU is logically enabled, and when said CPU-enabled flag for said CPU has a second state, the CPU is not logically enabled; and
a queue including control blocks for executable threads, wherein said control blocks includes control blocks for idle threads and further wherein at least one of said control blocks for idle threads has a high idle execution priority.
13. A structure comprising:
a plurality of central processing units in a symmetric multiprocessing system; and
means for safely shutting down a central processing unit in said plurality of central processing units, said means further comprising:
means for setting an execution priority of an idle thread to other than a lowest priority.
14. The structure of claim 13 wherein said means for safely shutting down a central processing unit further comprises:
means for identifying a logically enabled state of said central processing unit.
15. The structure of claim 14 wherein said means for identifying a logically enabled state of said central processing unit is included in an idle thread executed by said central processing unit.
16. The structure of claim 13 wherein said means for setting an execution priority of an idle thread is included in a heuristic procedure executed by said central processing unit.
17. A process comprising:
assigning a first execution priority to one idle thread executed in a symmetric multiprocessor system wherein execution of said one idle thread with said first execution priority by a central processing unit in said symmetric multiprocessor system results in said central processing unit idling; and
assigning a second execution priority, different from said first execution priority, to said idle thread wherein execution of said idle thread with said second execution priority results in shutting down said central processing unit.
18. The process of claim 17 further comprising
assigning uninterruptible threads an execution priority higher than said second execution priority.
19. The process of claim 17 further comprising
assigning user mode tasks an execution priority between said first and second execution priorities.
20. A process comprising:
assigning a first execution priority to one idle thread executed in a symmetric multiprocessor system wherein execution of said one idle thread with said first execution priority by a central processing unit in said symmetric multiprocessor system results in said central processing unit idling;
assigning a second execution priority, different from said first execution priority, to said idle thread wherein execution of said idle thread with said second execution priority results in shutting down said central processing unit;
assigning uninterruptible threads an execution priority higher than said second execution priority; and
assigning user mode tasks an execution priority between said first and second execution priorities.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A lighting system comprising:
an electric lamp (1), which has a first (11) and at least one second lamp filament (12);
an electronic ballast (2), which is electrically connected to the lamp filaments (11, 12); and
at least two further light sources (31a to 31c; 32a to 32c), which are connected in a parallel circuit (3) with one another,
wherein the parallel circuit (3) comprising the two further light sources (31a to 31c; 32a to 32c) is connected in series between the first (11) and the second lamp filament (12).
2. The lighting system as claimed in claim 1, wherein the at least two further light sources (31a to 31c; 32a to 32c) are electrically connected to a first terminal (11a) of the first lamp filament (11) and a first terminal (12a) of the second lamp filament (12).
3. The lighting system as claimed in claim 1, wherein, the electronic ballast (2) is electrically connected to a second terminal (11b) of the first lamp filament (11) and to a second terminal (12b) of the second lamp filament (12).
4. The lighting system as claimed in claim 1, wherein the two further light sources (31a to 31c; 32a to 32c) are in the form of LEDs and are connected in phase opposition to one another into the respective signal paths (31, 32) of the parallel circuit (3).
5. The lighting system as claimed in claim 1, wherein a lamp filament preheating means (4) is connected in series with the parallel circuit (3) comprising the two further light sources (31a to 31c; 32a to 32c).
6. The lighting system as claimed in claim 5, wherein the lamp filament preheating means (4) is electrically connected to the first terminal (12a) of the second lamp filament (12).
7. The lighting system as claimed in claim 5, wherein the lamp filament preheating means (4) has a reactance (41), in particular a capacitor.
8. The lighting system as claimed in claim 1, wherein a switch (5) is connected in parallel with the parallel circuit (3) comprising the further light sources (31a to 31c; 32a to 32c).
9. The lighting system as claimed in claim 1, wherein a reactance (6), is connected in parallel with the parallel circuit (3) comprising the further light sources (31a to 31c; 32a to 32c).
10. The lighting system as claimed in claim 9, wherein said reactance is a capacitor.