1. A method of providing through-wafer interconnections in a semiconductor wafer having first and second sides, the method comprising:
etching one or more micro-vias in the second side of the wafer;
providing an etch stop layer over the second side, wherein the etch stop layer covers surfaces in the one or more micro-vias;
etching a cavity in the first side of the wafer to a depth such that portions of the etch stop layer, in areas where the one or more micro-vias were etched, are exposed in the cavity;
depositing metallization over one side of the wafer;
subsequently removing regions of the etch stop layer from areas corresponding to where the one or more micro-vias were etched; and
depositing metallization over the other side of the wafer so that the metallization deposited over the first side is in contact with the metallization deposited over the second side to form the through-wafer interconnections in areas corresponding to where the one or more micro-vias were etched.
2. The method of claim 1 wherein the semiconductor wafer comprises silicon, and the etch stop layer comprises at least one of silicon dioxide or silicon nitride.
3. The method of claim 1 wherein the semiconductor wafer comprises silicon, and wherein providing an etch stop layer includes thermally growing a silicon dioxide layer.
4. The method of claim 1 wherein a dimension of the cavity is larger than a corresponding dimension of each of the one or more micro-vias.
5. The method of claim 1 wherein the cavity in the first side of the wafer is etched to a depth so as to expose thin membranes of the etch stop layer in the cavity.
6. The method of claim 1 including etching the cavity to a depth such that a sum of the depth of the cavity and an average depth of the one or more micro-vias exceeds the total thickness of the wafer.
7. The method of claim 1 including providing an isolation layer over surfaces of the semiconductor wafer prior to depositing metallization over the one side of the wafer.
8. The method of claim 1 including:
selectively growing an oxide layer over the first and second sides of the wafer after etching the cavity in the first side, such that portions of the etch stop layer remain exposed in the cavity, and wherein the thickness of the oxide layer is greater than the thickness of the etch stop layer; and
wherein removing regions of the etch stop layer includes using an etchant that etches both the etch stop layer and the oxide layer.
9. The method of claim 8 including thermally growing the oxide layer.
10. The method of claim 8 wherein the oxide layer is at least three times as thick as the etch stop layer.
11. A method of providing through-wafer interconnections in a semiconductor wafer having first and second sides, the method comprising:
etching a cavity in the first side of the wafer;
providing an etch stop layer over the first side of the wafer, wherein the etch stop layer covers surfaces in the cavity;
etching one or more micro-vias in the second side of the wafer to a depth such that the one or more micro-vias reach the etch stop layer;
depositing metallization over one side of the wafer;
subsequently removing regions of the etch stop layer from areas corresponding to where the one or more micro-vias were etched; and
depositing metallization over the other side of the wafer so that the metallization deposited over the first side is in contact with the metallization deposited over the second side to form the through-wafer interconnections in areas corresponding to where the one or more micro-vias were etched.
12. The method of claim 11 wherein the semiconductor wafer comprises silicon, and the etch stop layer comprises at least one of silicon dioxide or silicon nitride.
13. The method of claim 11 wherein the semiconductor wafer comprises silicon, and wherein providing an etch stop layer includes thermally growing a silicon dioxide layer.
14. The method of claim 11 wherein a dimension of the cavity is larger than a corresponding dimension of each of the one or more micro-vias.
15. The method of claim 11 wherein the one or more micro-vias are etched to a depth so as to expose thin membranes of the etch stop layer in the cavity.
16. The method of claim 11 including providing an isolation layer over surfaces of the semiconductor wafer prior to depositing metallization over the one side of the wafer.
17. The method of claim 11 including:
selectively providing an oxide layer over the first and second sides of the wafer after etching the micro-vias in the second side, such that portions of the etch stop layer remain exposed in the cavity, and wherein the thickness of the oxide layer is greater than the thickness of the etch stop layer; and
wherein removing regions of the etch stop layer includes using an etchant that etches both the etch stop layer and the oxide layer.
18. The method of claim 17 including thermally growing the oxide layer.
19. The method of claim 17 wherein the oxide layer is at least three times as thick as the etch stop layer.
20. A method of providing through-wafer interconnections in a semiconductor wafer having first and second sides, the method comprising:
providing an etch stop layer on the second side of the semiconductor wafer;
etching an opening in the first side of the wafer so as to expose portions of the etch stop layer;
depositing metallization over one side of the wafer;
subsequently removing regions of the etch stop layer corresponding to the opening; and
depositing metallization over the other side of the wafer so that the metallization deposited over the first side is in contact with the metallization deposited over the second side to form the through-wafer interconnections in areas corresponding to where the opening was etched.
21. The method of claim 20 including providing an isolation over surfaces of the semiconductor wafer before depositing metallization over the one side of the wafer.
22. The method of claim 20 including:
selectively providing an oxide layer over the first and second sides of the wafer after etching the opening in the first side, such that portions of the etch stop layer remain exposed to the opening in the first side, and wherein the thickness of the oxide layer is greater than the thickness of the etch stop layer; and
wherein removing regions of the etch stop layer includes using an etchant that etches both the etch stop layer and the oxide layer.
23. A method of providing through-wafer structures in a semiconductor wafer having first and second sides, the method comprising:
forming a sacrificial dielectric membrane in or on a pre-existing semiconductor wafer;
depositing metallization over one side of the wafer so as to cover exposed portions of the sacrificial membrane facing the one side of the wafer;
removing exposed portions of the sacrificial membrane facing the other side of the wafer; and
depositing metallization over said other side of the wafer so as to contact the previously deposited metallization.
24. The method of claim 23 wherein the sacrificial membrane comprises at least one of silicon dioxide or silicon nitride.
25. The method of claim 23 wherein removing exposed portions of the sacrificial membrane includes etching the exposed portions.
26. The method of claim 23 including patterning the metallization to form an inductor.
27. The method of claim 23 including patterning the metal membrane to form a movable cantilever structure.
28. The method of claim 23 wherein only some of the exposed portions of the sacrificial membrane that face the other side of the wafer are removed, the method further including patterning the metallization to form a plurality of electrical interconnections through a single hermetic via in the semiconductor wafer.
29. A method of providing a capacitive structure in a semiconductor wafer having first and second sides, the method comprising:
etching one or more micro-vias in the second side of the wafer;
providing an etch stop layer over the second side, wherein the etch stop layer covers surfaces in the one or more micro-vias;
etching a cavity in the first side of the wafer to a depth such that portions of the etch stop layer, in areas where the one or more micro-vias were etched, are exposed in the cavity; and
depositing metallization over both sides of the wafer to form a capacitive structure comprising a portion of the etch stop layer sandwiched between layers of the metallization.
30. A method of providing a capacitive structure in a semiconductor wafer having first and second sides, the method comprising:
etching a cavity in the first side of the wafer;
providing an etch stop layer over the first side of the wafer, wherein the etch stop layer covers surfaces in the cavity;
etching one or more micro-vias in the second side of the wafer to a depth such that the one or more micro-vias reach the etch stop layer; and
depositing metallization over both sides of the wafer to form a capacitive structure comprising a portion of the etch stop layer sandwiched between layers of the metallization.
31. A method comprising:
forming a sacrificial membrane in a pre-existing semiconductor wafer;
depositing metallization over one side of the wafer so as to cover exposed portions of the sacrificial membrane facing the one side of the wafer;
removing exposed portions of the sacrificial membrane facing the other side of the wafer so that at least a portion of the metallization forms a metal membrane.
32. The method of claim 31 including patterning the metal membrane to form an inductor.
33. The method of claim 31 including patterning the metal membrane to form a movable cantilever structure.
34. A method of fabricating a package that houses a micro component, the method comprising:
forming a sacrificial membrane in a pre-existing semiconductor wafer;
depositing metallization over one side of the wafer so as to cover exposed portions of the sacrificial membrane facing the one side of the wafer;
removing exposed portions of the sacrificial membrane facing the other side of the wafer so that at least a portion of the metallization forms a metal membrane;
using the semiconductor wafer with the metal membrane as part of the package to house the micro component; and
using the metal membrane to evaluate the hermeticity of the package.
35. The method of claim 34 wherein evaluating the hermeticity of the package includes sensing changes in the shape of the metal membrane.
36. The method of claim 35 including using the changes to determine a relative pressure or leak rate.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A computer system having a removable processor board, comprising:
a latch circuit coupled to mechanical switch;
a controller coupled to the latch circuit; and
a processor coupled to the controller;
wherein the latch circuit is responsive to the mechanical switch to generate a latch signal.
2. The computer system of claim 1, wherein the controller is responsive to the latch signal to generate an interrupt signal.
3. The computer system of claim 2, wherein the processor is responsive to the interrupt signal to:
switch from a first operating mode to a second operating mode;
switch from the second operating mode to the first operating mode if a cause of the interrupt signal is determined to be the mechanical switch; and
notify at least one software component to shut down.
4. The computer system of claim 3, wherein the interrupt signal is a system management interrupt, the first operating mode is a protected mode, and the second operating mode is a system management mode.
5. A method for shutting down a computer system having a removable processor board, comprising:
generating a processor interrupt in response to an activation of a mechanical switch;
switching the processor from a first operating mode to a second operating mode in response to the processor interrupt;
determining a cause of the processor interrupt;
switching the processor from the second operating mode to the first operating mode; and
notifying a software component executing within the first operating mode to shut down;
wherein said notifying includes a message to the software component.
6. The method of claim 5, further comprising:
generating a latch signal in response to the activation of the mechanical switch; and
generating the processor interrupt in response to the latch signal.
7. The method of claim 5, wherein the processor interrupt is a system management interrupt, the first operating mode is a protected mode, and the second operating mode is a system management mode.
8. The method of claim 5, wherein said notifying includes writing a value to a location in memory.
9. The method of claim 5, wherein the first operating mode executes an operating system and the software component is an application program.
10. A method for restarting a computer system having a processor and a memory, comprising:
periodically storing system performance information in a memory;
generating a processor interrupt in response to a system anomaly, said processor interrupt is a system management interrupt;
switching the processor from a first operating mode to a second operating mode in response to the processor interrupt, said first operating mode is a protected mode and said second operating mode is a system management mode;
determining whether to restart the computer system based on the performance information; and
restarting the computer system if so determined.
11. The method of claim 10, further comprising:
associating at least one component of the computer system with the system anomaly based on the performance information;
determining whether to replace the component; and replacing the component if so determined.
12. The method of claim 11, wherein the component is a hardware device.
13. The method of claim 11, wherein the component is a removable processor board.
14. The method of claim 10, further comprising:
associating at least one component of the computer system with the system anomaly based on the performance information;
determining whether to restart the component; and restarting the component if so determined.
15. The method of claim 14, wherein the component is the processor.
16. The method of claim 14, wherein the component is a software process executing within the first operating mode.
17. The method of claim 14, wherein the component is a software process and said restarting the component includes:
switching from the second operating mode to the first operating mode; and
notifying an operating system executing within the context of the first operating mode to restart the software process.