1. A digital circuit comprising:
a fetchdecode unit that receives an instruction stream that includes a floating point save instruction, the fetchdecode unit generating a floating point address save microinstruction and a floating point data save microinstruction corresponding to the floating point save instruction;
a floating point linear address register; and
a floating point execution unit coupled to the floating point linear address register, the floating point execution unit using the floating point linear address register in executing floating point instructions,
wherein an update of the floating point linear address register is triggered by the floating point store data microinstruction.
2. The digital circuit of claim 1 further comprising an event floating point linear address register, wherein the floating point store data microinstruction triggers the update of the floating point linear address register or the event floating point linear address register.
3. The digital circuit of claim 1 further including a memory order buffer, the memory order buffer maintaining information pertaining to load and store instructions,
wherein the memory order buffer updates the floating point linear address when triggered by the execution of the floating point store data microinstruction.
4. The digital circuit of claim 3 wherein the information pertaining to load and store operations maintained by the memory order buffer includes for each load and store instruction:
an operation type field;
an address field; and
a store identifier field.
5. The digital circuit of claim 4 wherein the operation type field indicates whether the instruction is a load instruction or a store instruction.
6. The digital circuit of claim 3 wherein the floating point store data microinstruction triggers update of the floating point linear address by writing fault information.
7. The digital circuit of claim 1 wherein the floating point linear address register is a microinstruction-level register.
8. A method comprising:
receiving a floating point store instruction;
generating a floating point store address microinstruction;
generating a floating point store data microinstruction;
executing the floating point store address microinstruction and the floating point store data microinstruction, the floating point store data microinstruction triggering the update of a floating point linear address register; and
updating a floating point linear address register when triggered by the execution of the floating point store data microinstruction.
9. The method of claim 8 wherein the step of updating a floating point linear address register includes updating an event floating point linear address register if an event is being handled.
10. The method of claim 8 wherein the steps of generating a floating point save address microinstruction and generating a floating point save data microinstruction are performed by a fetchdecode unit.
11. The method of claim 8 wherein the step of updating the floating point linear address register is performed by a memory order buffer.
12. The method of claim 11 wherein the memory order buffer maintains the following information for each load and store operation:
an operation type field;
an address field; and
a store identifier field.
13. The method of claim 8 wherein the floating point store data microinstruction triggers the update of the floating point linear address register by writing fault information.
14. A method comprising:
receiving an instruction stream including a floating point store data instruction;
generating a floating point store data microinstruction corresponding to the floating point store data instruction;
generating a floating point store address microinstruction, the floating point store data microinstruction and the floating point store address microinstruction including a sequence number; and
in response to the execution of the floating point store data microinstruction, updating a floating point linear address using the sequence number corresponding to the floating point store address microinstruction.
15. The method of claim 14 wherein the steps of generating a floating point store data microinstruction and generating a floating point store address microinstruction are performed by a fetchdecode unit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A connection element for connecting media lines, for instance hoses to a tube piece, in particular a tube, wherein at least a first plug-shaped connection member (3) having at least two hose connections (1,2) is provided, whose plug part includes axially offset, radial openings (6,7) each connected with a hose connection (1,2), and wherein at least one socket-shaped connection member (26) is provided for receiving the plug-shaped connection member (3) in a manner rotational about the plug-in axis (8), the wall of which socket-shaped connection member likewise includes radial openings (14,15) at axial distances corresponding with the axial distances of the radial openings (6,7) of the plug-shaped connection member (3), wherein the walls of the socket-shaped and the plug-shaped connection members (3, 26) include annular or disc-shaped seals (18) sealing relative to each other between adjacent radial openings (6,7,14,15) as well as to the axial end of the socket-shaped (26) andor plug-shaped connection member (3), characterized in that the plug-in depth of the plug-shaped connection member (3) is limited by resilient stops (12) and the resilient stops (12) are designed as resilient: Locking members latching with counter stops (22,23)
2. A connection element according to claim 1, characterized in that the radial openings (6,7,14,15) are comprised of annular grooves or open into annular grooves (16, 17).
3. A connection element according to claim 1, characterized in that 0-rings seals (18) are arranged between adjacent annular grooves (16, 17) and outside the same.
4. A connection element according to claim 1, characterized in that connection boxes carrying the socket-shaped connection members (26) are provided for the supply of gas.
5. A connection element according to claim 1, characterized in that, for a number of hose connections (1,2) exceeding the number of hose connections fixable to a first plug-shaped, or the respective socket-shaped, connection member (3,26), further plug-shaped and socket-shaped connection members (3,26) having outer and inner diameters respectively differing from those of the first connection members are provided.